Compute architecture

Chiplets, UCIe, CFET, GAA nanosheet, FD-SOI, backside power delivery, cryo-CMOS. How transistors are arranged once you can't shrink them any further.

24 concepts in this cluster

3D Monolithic Integration

3 frontier questions

ADC Bottleneck (analog in-memory compute)

3 frontier questions

AI Compiler & Heterogeneous Programming-Model Landscape

3 frontier questions

Apache TVM

2 frontier questions

Backside Power Delivery (BPD)

1 frontier question

CFET (Complementary FET)

1 frontier question

Chiplets

1 frontier question

Compiler as Bottleneck for Novel Hardware

3 frontier questions

Cryo CMOS

1 frontier question

Dennard Scaling

1 frontier question

FD-SOI

+7 sources in 30d

GAA / Nanosheet Transistor

1 frontier question

HBM / CoWoS Bottleneck

4 frontier questions

IREE (Intermediate Representation Execution Environment)

2 frontier questions

Mature Foundry Positioning

3 frontier questions

MLC-LLM (Machine Learning Compilation for LLMs)

1 frontier question

MLIR (Multi-Level Intermediate Representation)

2 frontier questions

Moore's Law

1 frontier question

The Memory Wall

2 frontier questions

Triton (OpenAI Triton)

2 frontier questions

UALink (Ultra Accelerator Link)

2 frontier questions

UCIe (Universal Chiplet Interconnect Express)

1 frontier question

Von Neumann Bottleneck

1 frontier question

XLA / OpenXLA

2 frontier questions