CHERI (Capability Hardware Enhanced RISC Instructions)

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last updated 2026-06-23 · +1 sources in last 30d
TEETEECHERI (Ca…

A hardware architecture for memory safety, developed at the University of Cambridge and SRI International (with DARPA funding from ~2010). CHERI makes every pointer a hardware-enforced capability: a fat pointer carrying bounds and permissions, validated in silicon on every memory access, with an unforgeable tag bit. The result is deterministic, hardware-enforced spatial and temporal memory safety for C/C++ code, plus fine-grained software compartmentalisation, without rewriting the code.

CHERIoT is Microsoft Research’s variant for tiny embedded cores (built on the lowRISC Ibex RV32E core), adding compartmentalisation primitives and an open-source RTOS. It is the lineage SCI Semiconductor commercialises in its ICENI microcontrollers.

Why it matters

Roughly 70% of serious security vulnerabilities are memory-safety bugs (Microsoft / Google / US ONCD data). The policy world’s primary fix is memory-safe languages (Rust); CHERI is the hardware path, valuable for the trillions of lines of legacy C/C++ firmware that will never be rewritten. It is a different primitive from confidential computing / TEEs (which protect data in use from a privileged host), and the two are sibling hardware-security mechanisms — see Hardware Memory Safety and Confidential Computing.

How it differs from the alternatives

The adoption tax: it requires new silicon and a recompiled toolchain, which is the central reason its commercialisation is slow.

Ecosystem

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