Physics / mechanism
Hardware software co-design covers the layer where a silicon part and the software that drives it are specified against each other rather than sequentially. In practice the coupling point for embedded systems is the board support package: the drivers, clock and pin configuration, memory maps and register definitions that let an operating system address a specific chip on a specific board. That layer is derived from vendor documentation, and its correctness is a function of how faithfully register offsets, bitfields, errata and peripheral semantics are transcribed from prose and tables into code.
Key parameters for any system of this shape are extraction fidelity per document type, coverage across chip families and peripheral classes, whether the structured model stays stable as errata accumulate, and whether generated code passes the same validation and certification path as hand-written drivers.
Competitive landscape
Evidence base
Frontier (open questions)
- What is the measured extraction accuracy, per register and per peripheral, when the structured model is diffed against vendor-supplied SVD files or hand-written reference drivers?
- Do generated BSPs pass functional-safety qualification (for example the AUTOSAR and automotive toolchain requirements implied by the claimed targets) without manual rework, and has any customer shipped one?
- How does the model handle errata that contradict the primary reference manual, and is the conflict resolution auditable?
- What is the actual reduction in BSP bring-up time against a hand-written baseline on the same silicon, measured by an independent party rather than stated on the vendor site?
Synthesised 2026-08-31 from 1 KB sources by the resynth pipeline; citations are KB source slugs.