Physics / mechanism
CFET stacks nMOS and pMOS transistors vertically on the same footprint — n-type device on bottom, p-type on top (or inverted), sharing a common gate stack with separate source/drain contacts routed independently via backside power delivery. The key gain is cell area: a 2× standard-cell height reduction versus FinFET at equivalent logic density, enabling ~50% footprint shrink on inverters and NAND gates. Gate-all-around nanosheets (GAA/RibbonFET) are a prerequisite — CFETs are the next integration step beyond them. IMEC demonstrated functional CFET SRAM at 48nm contacted poly pitch in 2023; TSMC and Samsung are targeting sub-2nm-node insertion around 2027–2029.
Competitive landscape
The primary alternative is conventional co-planar CMOS scaling with GAA nanosheets (Intel 20A/18A, TSMC N2, Samsung SF2), which avoids CFET complexity at the cost of retaining separate n/p diffusion tracks. Forksheet FET is a direct competitor — it separates n/p by a dielectric wall on the same plane, simpler process than CFET but less area-efficient. Backside power delivery networks (BSPDN) are complementary infrastructure, not a substitute.
Companies using
Connected ideas
Sources
Frontier (open questions)
- To be added.