FD-SOI

last updated 2026-08-31
Assessment draft · unreviewed
Viability
5/5
Drivers
4/5
Novelty
2/5
Diffusion
3/5
Impact
3/5

Timing Now (0-2yr) · Read Underrated

FD-SOI is a planar CMOS process family built on a thin silicon layer over a buried oxide, sold by non-leading-edge foundries as a low-leakage, RF- and analog-friendly alternative to bulk CMOS and FinFET, and it has quietly become the default substrate for always-on edge silicon, embedded non-volatile memory and cryogenic quantum control chips.

Summary

FD-SOI (fully depleted silicon-on-insulator) is a manufacturing platform rather than a device concept. The transistor channel sits in a very thin silicon film separated from the bulk wafer by a buried oxide, so the channel is fully depleted without heavy doping and the substrate under the channel remains electrically accessible. The commercial instances that appear in the sources are GlobalFoundries’ 22FDX (22nm FD-SOI) and Samsung’s 28nm FD-SOI, with ST and GlobalFoundries running FD-SOI specialty work at Crolles under EU Chips Act alignment 2024 Eu Chips Act Final Text.

The practical consequences show up in the research literature. Because the PDK exposes transistor substrate terminals, designers can inject and measure substrate noise directly, which is how a 22nm FD-SOI ring VCO was used to characterise through-silicon-via coupling in 3D-IC stacks, yielding a -35.2 dBc sideband spur under a 1 GHz, 0.5 Vpp aggressor. The same platform is the vehicle for leakage-dominated always-on logic research, where feedforward leakage suppression logic is being explored specifically in FDSOI to cut standby power in the always-on domain of event-driven wearables and IoT devices. It is also where low-bit LLM accelerators are being prototyped: the AdaMX adaptive microscaling accelerator was implemented as a 22nm FD-SOI prototype.

Two commercial anchors matter more than the papers. First, embedded non-volatile memory: Samsung has mass-produced eMRAM on 28nm FD-SOI since 2019 and GlobalFoundries put eMRAM into production on 22FDX in February 2020, using perpendicular-MTJ STT-MRAM licensed from Everspin, in 2 Mb to 32 Mb macros with >10-year retention at 125 °C and survival through 260 °C solder reflow ref. GF’s 2026 investor material lists a broad eNVM portfolio (eMRAM, ReRAM, Flash) across FDX, FinFET and BCD, with FDX as the lead platform, framed around “autonomous secure always-on AI-enabled IoT edge devices” and 39B+ connected IoT devices by 2030 ref. Second, cryogenics: GF states its FDX platform delivers the cryogenic CMOS used for sensing, control and readout in quantum systems, built on more than a decade of US Government-partnered work, and has a $375M Department of Commerce letter of intent tied to a ~1% strategic equity stake ref. Academic work corroborates the cryo path: CryoZip was implemented in 22nm FDSOI characterised at 4 K.

The deciding parameters are not transistor physics but platform economics: which nodes carry FD-SOI, which eNVM and RF options are qualified on them, whether the PDK exposes the back-gate/substrate for designers who want it, and whether cryogenic characterisation becomes a supported PDK corner rather than a one-off measurement campaign.

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Assessment drafted 2026-08-31 from up to 10 KB sources using the technology-scorecard framework; scores are a draft read pending review.

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