Compute-in-memory where the multiply-accumulate is done by analog physics inside the memory array, not by digital logic. The array holds the weights; apply the inputs as voltages or charges and read the summed current or charge, and the matrix-vector multiply happens in one physical step (Ohm and Kirchhoff for resistive devices, charge-sharing for capacitive).
The energy ceiling, and its tax
Analog AIMC offers the highest theoretical efficiency (100+ TOPS/W claimed) because it collapses the Von Neumann Bottleneck: no weight movement, the MAC happens in place. The catch is the ADC Bottleneck (analog in-memory compute) (every analog result must be digitised, and the converters dominate area and power), plus limited effective precision (~4 to 6 bit), device variability, and conductance or charge drift. Those are the reasons analog CIM has stayed edge-bound through roughly 2029 (see Hbm Free Inference Architectures).
Sub-families
Contrast Digital In-Memory Compute (digital MAC, no ADC tax, lower ceiling, production-ready).
Cluster role
Hand-authored synthesis, 16 June 2026.