Analog in-memory compute performs matrix multiplication inside the memory array itself by exploiting device physics rather than moving data to a logic unit, and 2026 research shows it works on fabricated silicon for weight-stationary layers while still fighting drift, update asymmetry and noise on anything dynamic.
Summary
The device layer is plural and unsettled. Resistive crossbars are the classical substrate and underpin the analog training and MIMO work. Single-poly floating-gate arrays can be built in a standard 65 nm CMOS flow. Charge-based devices avoid resistive read current entirely: the memcapacitor was proposed on exactly that basis Demasius 2021 Memcapacitor Nature Electronics, and HfO2/ZrO2 ferroelectric capacitors have been integrated in the BEOL of CMOS with multilevel switching below 5 V, endurance above 10^11 cycles and 10-year retention.
The parameters that decide the technology are not peak efficiency but the non-idealities. Retention: floating-gate cells drift, and 60 days after programming inference accuracy on VGG-10/CIFAR-10 and WideResNet-28-10/CIFAR-100 only returns to within 2-4% of baseline after circuit-level compensation plus batch-norm recalibration. Update asymmetry: repeated programming drifts weights towards a device-specific symmetric point that is not the training optimum, and calibrating that point costs pulses. Read speed: the ferroelectric memcapacitance window collapses above 1 MHz read frequency, which is why the authors resort to 20 ps pulses reading polarisation-dependent leakage instead. Workload fit: analog CIM suits weight-stationary linear layers, and the KV cache of an LLM, which demands repeated in-situ weight updates, does not fit that paradigm at all.
Everything in the current literature therefore points at hybrid systems rather than all-analog ones: heterogeneous chiplet architectures mixing analog CIM, digital CIM and intermediate data processing, and schedulers that keep the noise-sensitive parts of a workload on a higher-precision digital path.