Physics / mechanism
Resistive RAM stores data by switching a thin dielectric (typically HfO₂, TaO_x, or Al₂O₃) between high-resistance (HRS) and low-resistance (LRS) states via controlled filament formation and rupture. An applied voltage drives oxygen vacancy migration, forming or dissolving a conductive filament—SET operation ~1 V, RESET ~1–2 V, switching <10 ns, endurance 10⁶–10¹² cycles depending on material stack. Retention >10 years at 85 °C for mature nodes. Cell area as small as 4F². Multi-level cell (MLC) operation enables 2–3 bits/cell. Leading process nodes: TSMC 28 nm embedded RRAM in production; GlobalFoundries exploring integration at 22FDX. Key players: Weebit Nano, Crossbar, CXMT, Ememory, Panasonic.
Competitive landscape
RRAM competes primarily with embedded Flash (eFlash), MRAM, and PCM for NVM applications.
Companies using
Connected ideas
Sources
Production status: three forks (4 Jun 2026)
“Is ReRAM scalable” has three answers, because ReRAM is three bets (full synthesis: 2026 06 04 Reram Scalability What It Enables):
Frontier (open questions)
See frontmatter frontier: block. Key resolution markers:
- 2027: does binary/digital ReRAM-CIM outnumber analog multi-level parts reaching silicon for edge inference? (tracked as a prediction on Emerging Nvm)
- 2027: does a startup ReRAM process get publicly designed into a major foundry’s embedded-NVM roadmap (Intrinsic/GF materialises)?
- 2028: does any analog multi-level ReRAM-CIM vendor reach $100M cumulative product revenue, or is the analog fork a confirmed dead end?
2026 update: the digital-readout shift
Source: 2026 06 16 Cim Landscape 2026.