MRAM stores bits as the magnetic orientation of a nanoscale magnetic tunnel junction, and is being pushed as a non-volatile, near-zero-leakage replacement for SRAM caches and as a substrate for in-memory computing, but write energy and read/write error rates remain the binding constraints.
Summary
Magnetoresistive RAM (MRAM) stores each bit in a magnetic tunnel junction (MTJ): two ferromagnetic layers separated by a thin MgO barrier. When the free layer’s magnetisation is parallel to the fixed reference layer the junction resistance is low; when antiparallel it is high. The ratio between the two states is the tunnel magnetoresistance (TMR), and it sets how easily a sense amplifier can tell a 1 from a 0. Modern cells use perpendicular magnetic anisotropy (PMA) so the magnetisation points out of plane, which allows scaling to small diameters while keeping enough thermal stability for retention.
The write mechanism defines the variants. In STT-MRAM, current passed through the junction itself carries spin angular momentum that torques the free layer; this is the mainstream approach and is described in the literature as the leading candidate to replace SRAM in on-chip caches on the strength of near-zero leakage power, higher density, non-volatility and immunity to radiation-induced upsets. Because write and read share the same current path, reads can accidentally flip the bit: the read disturbance error. In SOT-MRAM, write current runs through an adjacent heavy-metal line and injects spin current sideways, decoupling read from write, at the cost of a larger (typically three-terminal) cell; two-terminal SOT variants are under study to recover density. A third route uses voltage-controlled magnetic anisotropy (VCMA), where a gate field rather than a current lowers the switching barrier.
The parameters that decide the technology are: write energy per bit and write pulse length; write error rate at that pulse length; TMR and hence sense margin; read disturbance rate; endurance; and the resistance-area (RA) product of the barrier, which trades off read signal against write current density. These are not independent. Raising RA to strengthen VCMA suppresses STT and Joule contributions and changes the switching physics entirely, which is why RA is used experimentally to separate the three mechanisms. Similarly, shortening the DC write pulse improves endurance but pushes up write error rate unless the switching is assisted, for example by a prior radio-frequency spin-torque pulse or by shaping the STT pulse in combined SOT+STT field-free schemes.
Evidence base
- Experimental MTJs with Ir remote doping near the MgO-CoFeB interface switched at 3.5 fJ per bit in the sub-nanosecond regime while retaining TMR up to 160 per cent after 400 C annealing (published 2025-11-22).
- Benchmarking published 2025-12-05 found that in-plane-torque SOT materials give little to no write-energy improvement over STT-MRAM; only out-of-plane torque with efficiency 0.051 at 20 nm widths brings write energy near SRAM at the 7 nm node.
- Work published 2026-01-01 formulated read disturbance accumulation from parallel cache-set reads and showed it significantly increases STT-MRAM cache error rate under conventional ECC-on-request schemes; a related scheme cut tag-array read disturbance rate by 71.8 per cent in gem5 simulation (published 2025-11-27).
- Field-free combined SOT+STT switching in top-pinned devices showed STT-induced backhopping and an intermediate loss-of-determinism regime; STT pulse shaping experimentally reduced write error rate (published 2026-04-24).
- An event-driven spiking SOT-MRAM compute-in-memory macro designed in 28 nm reported peak 243.6 TOPS/W by replacing analogue circuitry with spike encoding (published 2025-11-05).
- MTJ true random number generators reached 0.5 to 1 Gb/s per superparamagnetic device with NIST SP800 validation and sub-0.01 square micrometre footprints, using flows compatible with embedded STT-MRAM (published 2025-09-16).
- Cross-coupled STT-MRAM bitcells lifted the bitcell high-to-low current ratio to up to 8000, giving up to 3.86x sense margin and 27.6 per cent read disturb margin improvement over standard MRAM in-memory-computing arrays (published 2026-04-06).
Open questions
- Can any real material deliver out-of-plane SOT efficiency near 0.05 at 20 to 30 nm device widths, which is the condition on which the 2T-SOT write-energy advantage over STT depends?
- Do the architectural fixes for read disturbance accumulation (selective tag comparison, per-read ECC discipline) hold up in measured silicon rather than gem5 simulation, and what is their true area and latency cost?
- Does the 3.5 fJ per bit VCMA switching result survive transfer from single junctions to full arrays with process variation, and at what write error rate?
- Do cross-coupled bitcells that lift the high-to-low current ratio to 8000 cost enough area to erase MRAM’s density advantage over SRAM for in-memory computing?
Assessment drafted 2026-08-31 from up to 18 KB sources using the technology-scorecard framework; scores are a draft read pending review.