Summary
Evidence base
Open questions
Assessment drafted 2026-08-31 from up to 13 KB sources using the technology-scorecard framework; scores are a draft read pending review.
Memcapacitor
Cross-cuts: Compute
Assessment draft · unreviewed
- Viability
- 2/5
- Drivers
- 3/5
- Novelty
- 3/5
- Diffusion
- 2/5
- Impact
- 4/5
Timing Later (5-10yr) · Read Too early to say
Recent mentions
- The Memory Trade Isn't Over: Weights and KV Cache
- Positron AI research sprint: architecture, funding, customers, manufacturing
- The Once and Future Kimi
- The Path To AGI Runs Through HBM
- Deep research: measured vs claimed inference-silicon economics (adversarially verified, 23/25 claims confirmed)
- ECTC 2026 Roundup: EMIB-T Roadmap, Custom HBM, HBM4 Packaging Challenges, Microfluidic Cooling, Photonic Interconnects, and More
- Compute-in-memory landscape 2026: efficiency claims, the digital-readout shift, IDM PIM
- Fungible Compute, Mortal Computing and Why the IoT won't use Silicon
Related concepts
Frontier questions
- Has any memcapacitor array been fabricated below the 50 x 50 µm cell size of the 2021 device, and what is the measured energy per MAC at that size rather than the extrapolated figure?
- Does the 95% charge-recovery assumption, worth 17.4x in the founding paper's efficiency grid, survive measurement in a real adiabatic driver circuit attached to a memcapacitor crossbar?
- Can a ferroelectric HZO memcapacitor hold multi-level analogue state with the retention, endurance and cycle-to-cycle linearity that FCDC's simulations assume, and for how long relative to a serving session?
- If the field standardises on digital readout with reduced effective precision, does the memcapacitor's charge-domain advantage survive the conversion overhead, or does non-volatility alone justify it against switched-capacitor SRAM?
- Does SEMRON's 3D monolithic CapRAM growth scale at production yield by 2027? (Most binding technical risk for the architecture class.)
- ADC overhead — does the analog→digital conversion cost at column ends cap practical performance, as it has constrained RRAM- and PCM-based IMC?
- Retention and endurance at standard CMOS interface — does charge-trapping suffer the same drift problems as floating-gate flash, or stay clean because the read mode is non-destructive?
- Process portability — does the device work at a single foundry process node (TSMC N16/N12, GF 22FDX) or does it need bespoke fab integration that locks in single-sourcing?
- Temperature calibration — does CapRAM compute accuracy drift across operating temperature in ways that need on-chip compensation circuitry, eating into the energy advantage?
- Competitive cliff with FeFET — does the FeFET roadmap (HfO₂-based, GlobalFoundries 22FDX-FeFET, Sony) close the manufacturing-readiness gap before memcapacitor reaches HVM?
- Application boundary — does the architecture stay edge-only (constrained by ADC overhead at large arrays), or does it scale to LLM decode workloads at hyperscaler volume?