Memristors are two-terminal devices whose resistance retains a memory of past electrical stimulus, offering dense non-volatile memory and analogue in-memory computing, but the 2026 literature is still resolving the stochastic switching physics that limits array-level reliability.
Summary
The honest reading of this source set is a field that has working devices in many material systems and is simultaneously still writing papers to establish what physically happens during a switching event.
Evidence base
Open questions
Can filament formation be made deterministic enough for uniform multi-level analogue weights, given that as of 2026 charge transport is dominated by a small number of discrete filaments rather than uniform conduction?
How do the read/write and soft error mitigations for ReRAM and STT-RAM trade off in area and energy once applied at array scale, and does the density advantage over SRAM survive them?
Does any memristive implementation beat a digital CMOS baseline on energy per inference for the same task, a comparison absent from the current sources?
Do the CMOS-compatible integration routes, BEOL VO2 below 430 C and foundry photonic MEMS, reach production yields, or remain single-die demonstrations?
Assessment drafted 2026-08-31 from up to 14 KB sources using the technology-scorecard framework; scores are a draft read pending review.
Recent mentions
2026-08-07The Memory Trade Isn't Over: Weights and KV Cachesubstack
2023-09-08🔮E14: The Real AI Bottleneck: High Bandwidth Memory (HBM)substack
Frontier questions
Can filament formation be made deterministic enough for uniform multi-level analogue weights, given that as of 2026 charge transport is dominated by a small number of discrete filaments rather than uniform conduction 2026 05 05 investigation of filamentation in a siagcu memristors with a?
How do the read/write and soft error mitigations for ReRAM and STT-RAM trade off in area and energy once applied at array scale, and does the density advantage over SRAM survive them 2026 06 18 nanoscale memristive devices threats and solutions?
Does any memristive implementation beat a digital CMOS baseline on energy per inference for the same task, a comparison absent from the current sources?
Do the CMOS-compatible integration routes, BEOL VO2 below 430 C and foundry photonic MEMS, reach production yields, or remain single-die demonstrations 2026 07 23 monolithically integrated vo2 mott oscillators for energy ef 2026 07 27 micro electromechanical photonic integrated memristors?