Compute-in-memory that keeps the multiply-accumulate digital, performed by logic embedded in or tightly bound to the SRAM array rather than by analog summation. Because there is no analog step, it sidesteps the ADC Bottleneck (analog in-memory compute) and the precision, variability and drift problems of Analog In-Memory Compute.
The tradeoff
Digital IMC is production-ready and foundry-compatible (standard SRAM plus logic), with full numerical precision and deterministic behaviour. The price is that it is still bound by the CMOS energy floor, so its efficiency ceiling is lower than analog. It trades peak TOPS/W for manufacturability. This is the scalable, lower-risk cut of in-memory compute, and the one most likely to ship at volume first.
Cluster members
Cluster role
Hand-authored synthesis, 16 June 2026.