Trends›Transistor scaling is over

Transistor scaling is over

Classical Moore/Dennard cost-per-transistor scaling has effectively ended, so future chip performance gains must come from advanced packaging, new materials and architecture rather than from shrinking the transistor.

92 ↓1 confidence, computed 23 Oct 2026

Technical
High weight

Fig. 1The evidence leans for, overwhelmingly by weight, and the newest evidence points the same way.

Rests onfacts underneath

Dennard scaling has ended

What rests on thismarkets it underwrites or threatens

Threatens

Evidencethe schedule the figure draws

The evidence, newest first

Jul 2026
for · primary N2 wafers price at ~$30,000 against ~$20,000 at N3, a 50-66% rise, making N3->N2 the first major node transition where wafer cost per transistor RISES; cost per transistor has not fallen in over a decade. TSMC Price Hikes End the Era of Cheap Transistors (SemiWiki)
Jul 2026
for · observable A16 is reported at up to $45,000/wafer, ~50% above prior generation, with backside power delivery (BSPDN) adding process steps and cost rather than shrink delivering the gain. TSMC could charge up to $45,000 for 1.6nm (A16) wafers
Jun 2026
for · observable IBM's 0.7nm "Nanostack" research node doubles density over 2nm via 3D sequential integration and per-layer material heterogeneity, not lateral shrink, confirming gains now come from architecture/stacking. IBM debuts world's first sub-1nm chip technology (Nanostack)
Jun 2026
for · primary CoWoS demand runs 370k wafers (2024) -> 670k (2025) -> ~1M (2026), TSMC monthly CoWoS capacity reaches 120-140k wafers in 2026 (~200k industry-wide with OSATs) on a >80% CAGR 2022-27 — packaging absorbing the gains that shrink no longer delivers. TSMC CoWoS supply-demand gap seen narrowing from 20% to 10% by end-2026 (TrendForce)
Apr 2026
for · observable TSMC CoWoS capacity expanding from ~80k to 120-130k WPM through 2026 (~40% YoY) with a panel-level CoPoS pilot line — performance gains migrating to advanced packaging. TSMC CoWoS expansion + CoPoS pilot (TrendForce)
Feb 2026
for · observable N2 is TSMC's first GAA (nanosheet) node and A16 introduces backside power delivery (~8-10% speed / 15-20% power gain) — gains from architecture and BSPD, not shrink. TSMC N2 GAA + A16 backside power roadmap
Jan 2026
for · observable Advanced-packaging market ~$44-52B in 2026 growing to ~$66-94B by the early-2030s (~6-9% CAGR), driven by AI/HPC chiplet integration. 2026 advanced packaging outlook ~$44-52B (TechInsights)
Oct 2025
against · claim The N2 increase (10-20%) came well below the feared 50% — per-wafer cost escalation more contained than worst-case, though still rising. N2 hike came below feared 50% (TechNode)
Oct 2025
for · observable TSMC finalized N2 wafer pricing ~$30,000, a 10-20% rise over N3's $25,000-27,000 — the increase outpaces realistic density gains, lifting cost per transistor. TSMC sets 2nm wafer price at $30,000 (TechNode)
Oct 2025
for · primary EE Times: 'For the first time in a major node transition, the cost per transistor will rise' at N2, with N2 wafers ~$30,000 vs ~$20,000 for N3. TSMC price hikes end the era of cheap transistors (EE Times)

What would move itthe measures watched

watchTSMC leading-node wafer price (N3→N2→A16). Wafer price rising faster than density gain = cost/transistor scaling broken; flat/declining = scaling restored
watchCost-per-transistor trend at node transition. First rise in a major transition (N3→N2) confirms the thesis; renewed declines disconfirm
watchGAA / CFET / backside-power roadmap milestones. Architecture/packaging-led gains (GAA at N2, BSPD at A16) replacing pure shrink = thesis confirmed
watchAdvanced-packaging market size & growth (CoWoS, hybrid bonding). Packaging outpacing wafer-cost-of-shrink = value migrating to packaging