OSAT firms are the contract manufacturers that dice, package and test finished chips for others, and the AI-driven shift of packaging from a commodity step to a 2.5D/3D advanced-packaging market forecast at $80B by 2030 is the event that decides whether that tier gains or loses relevance.
Summary
OSAT stands for Outsourced Semiconductor Assembly and Test. It is a business model rather than a device technology. A foundry or an integrated device manufacturer produces and probes wafers; an OSAT then takes those wafers, dices them, attaches the die to substrates or interposers, forms the interconnect (wire bond, flip chip, fan-out redistribution layers, through-silicon vias, die stacking), encapsulates and finally tests the packaged units. Historically this was the low-margin end of the chain: labour and capital arbitrage on a step that added little differentiated value, which is exactly why it was outsourced.
What changes that is the shift of system-level performance from the transistor to the interconnect. Advanced packaging is measured as a distinct market growing at a 9.6% CAGR from 2024 to 2030 to reach $80B by 2030, with 2.5D/3D identified as the fastest-expanding platform and AI as the driver; quarterly revenue was $13B in Q2 2025 with 13% sequential growth projected for Q3 2025 ref. The packaging step is now capable of being the binding constraint on a product line rather than a cost line: SemiAnalysis models CXMT going from 1% of global HBM wafer supply in 2025 to 12% by 2028 and states that the bottleneck is no longer ambition or capital but HBM stacking yield.
The parameters that decide the OSAT tier specifically are not the growth of packaging but where in the flow the hard steps sit. Wire bond and flip chip are die-level operations that an OSAT owns. Hybrid bonding, wafer-to-wafer and die-to-wafer bonding, micro-transfer printing and monolithic BEOL integration are wafer-level processes that look and behave like front-end lithography and are being demonstrated inside CMOS foundries and pilot lines, for example a 200 mm CMOS pilot line using micro-transfer printing as a back-end post-processing step and foundry-compatible BEOL post-processing for photonic MEMS switches. Every step that migrates to wafer level migrates away from the OSAT floor.
One terminology warning, because it explains why the source base around this concept is thin. The semiconductor industry uses “back end” for assembly and test (the OSAT domain) and “back end of line” or BEOL for the metallisation layers built on top of transistors inside the wafer fab. Most of the tier-1 literature returned for this concept concerns BEOL integration of new materials (ferroelectrics, IGZO, VO2, lithium niobate, diamond heat spreaders) and says nothing about outsourced assembly. Those papers are relevant only indirectly, as evidence about where integration value is accumulating.
Viability (4/5)
There is no technical question to answer about whether packaging and test work: advanced packaging alone booked $13B of revenue in Q2 2025 and is on a 9.6% CAGR path to $80B by 2030 ref. The activity is in high-volume production and is being pulled forward by AI workloads. On that basis the function scores high.
The caveat is that none of the supplied sources measures the outsourced tier as such. No OSAT company, capacity figure, utilisation rate or margin appears anywhere in the source base. The score therefore reflects the viability of advanced assembly and test as a manufacturing activity, and should not be read as evidence that the third-party service model specifically is healthy. The one place the sources show packaging as a live technical risk is stacking yield, described as the bottleneck for CXMT’s HBM ramp; that is a real, current, unsolved process problem in exactly this domain.
TLDR: Assembly, test and advanced packaging are running at volume today; the sources evidence the market, not the outsourcing model.
Drivers (4/5)
Demand: advanced packaging grows at 9.6% CAGR to $80B by 2030 with 2.5D/3D the fastest-expanding platform driven by AI ref. Adjacent demand pulls point the same way: AI back-end network switch spending is forecast past $20B by 2028 and above $100B by 2030, 1.6 Tbps switches ship in volume in 2026, and co-packaged optics could add multiple further billions, with the market described as supply-constrained rather than demand-constrained ref. Co-packaged optics in particular is an assembly problem, and heterogeneous integration of new photonic materials is arriving as a post-processing step rather than a monolithic redesign. HBM stacking demand is a third pull, with CXMT modelled from ~5 kwspm of HBM capacity at end-2025 to ~100 kwspm by 2028.
Supply: the sources give nothing on assembly capacity, equipment lead times, substrate supply or test capacity, which are the usual constraints in this tier. There is one counter-driver worth logging. Monolithic 3D integration of larger caches at BEOL is being studied explicitly as a way to cut off-chip HBM traffic, with L2 expanded from 40MB upwards. Any success there substitutes wafer-level process for packaged bandwidth, i.e. it moves value upstream of the OSAT.
TLDR: Demand is well documented and AI-driven; supply-side evidence on assembly capacity is absent.
Novelty (2/5)
OSAT as such is better than nothing only in the trivial sense of being cheaper than owning your own assembly line, and the sources contain no cost, yield or cycle-time comparison between outsourced and in-house assembly. So the interesting novelty question is whether the OSAT tier owns the new processes. The evidence in this source base points the other way. The demonstrated frontier integration work is wafer-level and foundry-resident: trench-based die-to-wafer bonding of thin-film lithium niobate onto active silicon photonics, 200 mm photonic wafers built directly on completed CMOS driver wafers by BEOL processing, micro-transfer printing in a 200 mm CMOS pilot line, and crystal-ion-sliced GaP direct wafer bonding. Even the thermal-management work targets a BEOL thermal budget below 400C, reporting diamond films at 73 and 86 W/m/K, about two orders of magnitude above conventional dielectrics.
Where OSATs plausibly retain novelty is in die-level 2.5D/3D assembly, and the sources confirm that platform is the fastest-growing one ref and that hybrid-bonded memory chiplets are an assumed architecture in device-level design studies. That is enough to say packaging technology is moving fast; it is not enough to say the outsourced tier is the party doing the moving. Score 2 is a judgement about the model, not about packaging.
TLDR: The model is decades old and the novel steps in packaging are wafer-level, which is not where OSATs sit.
Diffusion (3/5)
Diffusion of the underlying activity is already high and accelerating: $13B in Q2 2025, 13% projected sequential growth, and a path to $80B by 2030 ref. The barrier is not customer willingness but process capability. Stacking yield is named as the limiting factor on an entire national HBM ramp, which is the kind of problem that tends to be pulled in-house by the memory maker rather than contracted out, because the yield learning is the product.
The second barrier is structural position. Europe is described as underperforming at converting semiconductor research into industrial leadership, with advanced packaging named as one of the “More than Moore” domains where positions are still forming and with gaps in funding velocity and exits. And in the adjacent optics build-out, the read is that the systems layer is incumbent-owned with only the optics and interconnect slice genuinely contestable ref. Both suggest that a contract assembly tier diffuses volume readily and differentiated value with difficulty. The sources do not resolve the split, hence 3 rather than higher or lower.
TLDR: Advanced packaging is diffusing fast, but the sources do not establish whether the outsourced tier or the foundries and IDMs absorb it.
Impact (4/5)
The impact of the function is large and demonstrable. An $80B market by 2030 growing faster than the leading-edge logic it serves ref and a stacking-yield constraint that gates a challenger’s entry into HBM together mean assembly is on the critical path for AI compute, not downstream of it. Co-packaged optics and 1.6 Tbps class switching add a second, independent pull on advanced assembly ref.
The unresolved half is capture. The market monitor is being used precisely to test a falsifier about whether value concentrates in OSAT assembly margins through 2028, which tells you the question is open and not yet answered by the data ref. Nothing in the sources shows OSAT pricing power, margin expansion or share gain. A high-impact chokepoint owned by someone else is not a high-impact investment. Treat the 4 as scoring the packaging step, with the OSAT-specific claim unproven.
TLDR: Packaging is now a chokepoint on AI hardware; whether that translates into OSAT-tier value is unevidenced.
Timing Now (0-2yr)
Advanced packaging was already a $13B-per-quarter business in Q2 2025 with double-digit sequential growth projected, and 2.5D/3D was already the fastest-expanding platform ref. HBM stacking yield is described as the current bottleneck on a capacity ramp running from 2025 through 2028, and 1.6 Tbps switches ship in volume in 2026 ref. There is no waiting period here.
The question that resolves over a longer horizon, roughly two to five years, is where the value settles. The wafer-level integration routes that compete with die-level assembly are at demonstration stage now, in pilot lines and single-wafer results, so their commercial impact on the assembly tier lands later in the decade rather than immediately.
TLDR: The advanced-packaging mix shift and the stacking-yield constraint are both live in 2026, not pending.
Overrated or underrated? Overrated
The packaging step is genuinely more important than the industry’s historical treatment of it, and the numbers support that: faster growth than logic wafers, AI as the driver, and a yield problem sitting on the critical path of a national memory programme ref. Where the story overreaches is the leap from “packaging matters more” to “the outsourced assembly tier captures the value”. Nothing in this source base supports that leap, and several strands work against it: the hardest new integration steps in the literature are wafer-level and are being executed in CMOS foundries and pilot lines; the yield learning that gates HBM is the memory maker’s own product knowledge; and in the closest analogous build-out the systems layer is judged incumbent-owned with only a narrow contestable slice ref.
The call is therefore about the investment narrative rather than the industry. As a piece of physical infrastructure, OSAT capacity is indispensable and correctly valued. As a thesis about margin migration towards contract assemblers, it looks overrated until someone produces the margin data. Note the honest limitation: this source base was assembled largely around BEOL wafer processing, not assembly and test, so the OSAT-specific evidence is thin and this verdict should be revisited against financial disclosures from the tier itself.
Prediction
Calendar-2028 advanced-packaging revenue will exceed $60B, keeping the market on or above the 9.6% CAGR path to $80B by 2030 reported in April 2026 ref.
Evidence base
- Advanced packaging grew at a 9.6% CAGR from 2024 to 2030 towards $80B by 2030, with 2.5D/3D the fastest-expanding platform driven by AI; Q2 2025 revenue was $13B with 13% sequential growth projected for Q3 2025 ref.
- SemiAnalysis models CXMT rising from 1% of global HBM wafer supply in 2025 to 12% by 2028, and states the bottleneck is no longer capital but HBM stacking yield.
- AI back-end network switch spending is forecast to pass $20B by 2028 and $100B by 2030, 1.6 Tbps switches ship in volume in 2026, and the market is supply-constrained rather than demand-constrained; the systems layer is judged incumbent-owned ref.
- A 200 mm CMOS pilot line demonstrated micro-transfer printing of active components onto dual-layer SiN as a wafer-scale back-end post-processing step, published August 2026.
- A zero-change foundry-compatible silicon photonics MEMS switch with over 30 dB extinction ratio, under 1.5 dB insertion loss and about 20 nW static power was produced using BEOL post-processing, August 2026.
- Monolithic 3D BEOL cache expansion from 40MB upwards is being evaluated as a route to cut off-chip HBM traffic in LLM serving, a substitution path that moves bandwidth value from packaging to wafer processing.
- A July 2026 report names advanced packaging among the “More than Moore” domains where competitive positions are still forming, alongside gaps in European funding velocity and exits.
Open questions
- What share of the $80B-by-2030 advanced-packaging market is booked by outsourced assemblers versus foundries and IDMs, and is that share rising or falling through 2028?
- Do hybrid bonding and die-to-wafer bonding settle inside wafer fabs, or do OSATs qualify them at volume and on cost?
- Is HBM stacking yield solved in-house by memory makers, or does it create a durable outsourced high-value test and stacking business?
- Are OSAT gross margins actually expanding with the 2.5D/3D mix shift, or is the mix shift being absorbed as capex intensity with flat margins?
Assessment drafted 2026-08-31 from up to 18 KB sources using the technology-scorecard framework; scores are a draft read pending review.