Physics / mechanism
Direct copper-to-copper bonding achieved by planarising dielectric (SiO₂ or SiCN) and Cu pad surfaces to sub-nanometre roughness (Ra < 0.5 nm), then annealing at 200–400 °C. At temperature, Cu atoms interdiffuse across the interface, eliminating the bond line entirely. Electrical resistance across the joint is near-bulk Cu; pitch scalability reaches <1 µm today (TSMC SoIC at ~9 µm pitch in HVM, research demos at 1–3 µm). Bandwidth density scales inversely with pitch squared—orders of magnitude beyond flip-chip bumps. Dielectric fusion bonds simultaneously, providing mechanical integrity and hermetic sealing. Key process parameters: surface activation (plasma or CMP), particle control (sub-10 nm), and anneal ambient.
Competitive landscape
| Approach | Min pitch | Electrical R | Thermal budget |
|---|---|---|---|
| Hybrid bonding (Cu-Cu) | <1 µm (lab), ~9 µm (HVM) | Near-bulk Cu | 200–400 °C |
| Micro-bump (SnAg) | ~20–40 µm | Higher (intermetallic) | ~260 °C reflow |
| TCB (Cu pillar) | ~10–20 µm | Moderate | ~250–300 °C |
Companies using
Connected ideas
Sources
Frontier (open questions)
- To be added.