Co-packaged optics moves the optical transceiver out of the front-panel cage and into the same package as the switch or accelerator die, and after years as a research programme it is now entering commercial switch products, with NVIDIA citing early-2026 availability for Quantum-X InfiniBand CPO and 2H 2026 for Spectrum-X Ethernet CPO ref.
Summary
In a conventional data centre switch, electrical signals travel from the ASIC across the printed circuit board to a front-panel cage holding a pluggable optical transceiver, where they are converted to light. At 800G and 1.6T per port, those centimetres of copper trace become the dominant cost in power and signal integrity. Co-packaged optics (CPO) eliminates the journey: the photonic integrated circuit (PIC), containing modulators, photodetectors and wavelength multiplexers, is mounted on the same substrate, interposer or 3D stack as the switch or compute die, with fibre attached directly to the package. The argument for it is that copper interconnect is running out of headroom at high symbol rates, so introducing optics into the scale-up network becomes, in the words of one recent survey, no longer optional but essential.
The engineering is a packaging problem more than a photonics problem. The parameters that decide it are: fibre-to-chip coupling (grating couplers must cover wide wavelength ranges with low loss, a design problem now being attacked with neural-network-driven optimisation); modulator choice and its temperature behaviour; and thermal coupling between a hot logic die and a temperature-sensitive PIC. The last is the sharpest constraint. Micro-ring resonators, favoured for their compactness and natural fit with dense wavelength-division multiplexing, drift with temperature: analysis of TSMC’s COUPE architecture cites a tolerance of around plus or minus 1.7 nm in resonant wavelength before bit error rate degrades measurably. That is why the field is simultaneously pursuing thermally robust modulator materials, with thin-film lithium tantalate shown to hold bandwidth and DC bias stability at 120°C (and a 10% reduction in Vπ at high temperature), positioning it for uncooled CPO operation.
There is no single winning device stack. Silicon photonics with germanium detectors provides the foundry base; thin-film lithium niobate has been heterogeneously integrated onto a foundry-compatible SiPh platform at imec for 320 Gb/s unamplified transmission with a 100 GHz Ge photodetector ref; barium titanate reached a 300mm high-volume-manufacturing-compatible integration process on silicon photonics in January 2026 ref; and VCSEL-based engines are argued to be the low-cost, low-latency, high-wall-plug-efficiency route for short-reach scale-up. Integration architectures are equally plural, from 2.5D optical interposers in SiON/Si carrying flip-chipped InP electro-absorption modulated lasers to 3D stacks inside 3.5D heterogeneous packages.
The honest counter-position within the field is that CPO is being treated as a component optimisation when it is an architectural commitment that redraws the boundary between photonics, electronics and system design, and that standardisation, serviceability and thermal-aware co-design, not device performance, will decide whether it moves from early deployment to widespread adoption.
Evidence base
- NVIDIA announced on 2 March 2026 early-2026 availability for Quantum-X InfiniBand CPO switches and 2H 2026 for Spectrum-X Ethernet CPO switches, backed by a reported $4B commitment ref.
- LightCounting (March 2026 release) forecasts LPO and CPO ports together exceeding 30% of total 800G and 1.6T ports deployed in 2026-2028 ref.
- Analysis of TSMC’s COUPE architecture at the A16 / 2 nm node states that a resonant wavelength deviation of merely +/- 1.7 nm in PIC-layer micro-ring resonators causes measurable BER degradation (18 May 2026).
- Pre-silicon co-simulation of Intel 3.5D packaging reports compensated CPO spectral drift below 0.36 nm, 21% of the stated TSMC tolerance budget, with silicon validation on Intel 18A still pending (30 June 2026).
- Thin-film lithium tantalate modulators retain electro-optic modulation and bandwidth with DC bias stability at 120°C, and show a 10% Vπ reduction at higher temperatures, supporting uncooled CPO operation (30 April 2026).
- A 2.5D co-packaged optical I/O chipset on a SiON/Si interposer with flip-chipped InP EMLs and photodetectors was experimentally demonstrated as a 400 Gb/s single-fibre transceiver (9 February 2026).
Open questions
- Does the predictive thermal compensation approach holding CPO spectral drift to 0.36 nm survive silicon validation on Intel 18A, or does micro-ring drift force a shift to thermally insensitive modulators such as thin-film lithium tantalate?
- In the LightCounting forecast of over 30% of 800G/1.6T ports for LPO plus CPO in 2026-2028, what is the CPO-only share, and does linear-drive pluggable optics cap CPO adoption at the switch?
- What is the field failure and repair model for a co-packaged optical engine, and has any hyperscaler accepted package-level RMA in place of transceiver swap?
- Do coherent CPO schemes such as offset-QAM-16 move from foundry-process simulation to measured hardware at 400 Gb/s per lane, and at what laser power and package temperature?
Assessment drafted 2026-08-31 from up to 18 KB sources using the technology-scorecard framework; scores are a draft read pending review.