Heterogeneous integration (HI) is the assembly of multiple distinct semiconductor dies — each optimised at a different process node, material system, or technology — into a single package that functions as a unified system. Unlike monolithic SoC integration, which forces all functional blocks onto one process node, HI allows logic, memory, RF, photonic, and analogue dies to be individually optimised (e.g., CMOS logic at 3 nm TSMC N3E, HBM DRAM at LPDDR-class stacked DRAM, RF front-end at GaAs or GaN) and then assembled via advanced packaging interconnects.
The enabling techniques span a spectrum of interconnect pitch and density. At the coarsest level, wire bonding and flip-chip with controlled-collapse chip connection (C4 bumps, ~100–150 µm pitch) are mature. Advanced HI moves to micro-bumps (~20–40 µm), copper pillars, and ultimately hybrid bonding (direct Cu-Cu thermocompression, sub-1 µm pitch, no solder) — enabling die-to-die interconnect bandwidths that approach monolithic integration. Silicon interposers, through-silicon vias (TSV / Through-Silicon Via), and silicon bridges (Intel EMIB) provide the routing fabric between dies. TSMC CoWoS (CoWoS (TSMC)), Samsung X-Cube, and Intel Foveros are the leading HI packaging platforms.
The investment logic for Chiplets Architecture Share is directly anchored in HI: the chiplet thesis is that monolithic die economics break at advanced nodes (reticle limits, yield curves, cost of single-node forcing), and HI provides the integration layer that makes disaggregated chiplet designs economically viable. The Brain Computer Interfaces frontier also touches HI: hybrid-bonded CMOS-on-CMOS stacks are being explored as the density mechanism for neural recording arrays. Deal-flow angles include HI substrate specialists, known-good-die test, yield analytics, and die-to-die interconnect IP.
Frontier
- What is the practical yield floor for heterogeneous integration of known-good-die at sub-10 µm bump pitch — is KGD test the binding constraint on cost?
- When do photonic chiplets enter heterogeneous integration production stacks alongside electronic logic and HBM?
- Does the CHIPS Act and EU Chips Act capex wave materially expand HI packaging capacity outside Taiwan and Korea by 2028?