Physics / mechanism
A Through-Silicon Via is a vertical electrical interconnect that passes completely through a silicon die or wafer. Etched by deep reactive-ion etching (Bosch process), lined with a dielectric (typically SiO₂, ~100–200 nm), barrier-seeded (Ta/TaN), and filled with electroplated copper or tungsten. Key parameters: via diameter (2–10 µm in leading-edge HBM stacks), aspect ratio (10:1–20:1), pitch (down to ~40 µm in HBM3), and RC parasitics. Bandwidth density exceeds 1 TB/s/mm² in HBM3 implementations. Thermal resistance and copper pumping (CTE mismatch-driven extrusion) remain the core reliability constraints. Via-last, via-middle, and via-first integration schemes each carry different cost and yield profiles.
Competitive landscape
Wire bonding (cheap, mature, ~100 MHz bandwidth ceiling) and embedded multi-die interconnect bridge (EMIB, Intel) are the primary alternatives. Fan-out wafer-level packaging (FOWLP/InFO, TSMC) avoids TSVs entirely for some 2.5D configurations. Hybrid bonding (Cu-Cu direct bonding, <10 µm pitch) is the successor technology for highest-density stacking and threatens TSV for leading-edge AI accelerator packages.
Companies using
Connected ideas
Sources
Frontier (open questions)
- To be added.