Theses›Semiconductor manufacturing›Photonic test and metrology

Photonic test and metrology

As CPO and silicon-photonics ramp, photonic test, known-good-die screening and active-alignment metrology become volume-gating (Teradyne flagged SiPh wafer/module test as the new bottleneck, Feb 2025).

  • Bear
  • Shut
  • $3.9B by 2035

The callCo-packaged optics makes photonic wafer test a volume step, but Teradyne, FormFactor and Keysight bought the tool layer before the volume arrived.

D1D2R1R2R3C1foragainst D1D2R1R2R3C1foragainst
Fig. 1The balance. Drivers and catalysts against restraints, each block sized by its weight; catalysts hang dashed because they have not happened yet, sized by their odds. It tips toward the restraints.
  1. D1Co-packaged optics in Rubin-generation racks turns photonic chips into a volume part, and electrical testers cannot see light, so every die needs an optical test step.
  2. D2There is no agreed test standard for an optical die and no active alignment fast enough for chiplet volume, which is whitespace with named demand.
  3. R1The incumbents own the tool layer and are adding photonic test to probers and testers they already ship, so a standalone photonic tester has nowhere to sit.
  4. R2The one opening, the alignment primitive, routes through packaging rather than standing alone as a tool business.
  5. R3The exits here have been small; ficonTEC went for about $160M.
  6. C1NVIDIA's Rubin-generation scale-up co-packaged optics ships in volume, making photonic wafer test a foundry step rather than a lab one.2028
Rests onthe beliefs underneath
Supported by · confidence
What would prove itdated tests, open and resolved
202720282029today1234predictionswatch 202720282029today1234predictionswatch
Fig. 2Each ring is a dated test: dashed while open, struck through when overdue, ticked or crossed once resolved.
  1. 1By end-2027 at least one dedicated photonic wafer/module-test or active-alignment product line or venture-backed entrant is named in a CPO / SiPh ramp — doubles as a sourcing trigger.Dec 2027 · open
  2. 2A dedicated photonic wafer or module test, or active-alignment, product line or venture-backed entrant named in a CPO ramp.Dec 2027 · open
  3. 3Photonic wafer/module test + active-alignment metrology becomes a named volume-gating step in CPO/SiPh ramp by 2028, with at least one new entrant raising on a photonic-KGD/ATE tool.Dec 2028 · open
  4. 4Photonic test named as the volume-gating step with at least one new entrant raising on it.Dec 2028 · open
Expressionslisted, private, technologies
Private · 3 private companies.

Teramount · Vanguard Automation · Kacentric Optics

5 more private companies tracked, not shown

Technologies
Who has already bet on itprivate rounds, from public sources

$1M raised by 1 company, $9M of it in the last three years. Wave under way: Large rounds in the last three years; the category is funded and getting crowded.

  • $1MKacentric Optics
    • Founded 2019
     Seed, Apr 2026 $1M (Bpifrance, Private investors (unnamed))
What changedthe record, newest first
  • 2 Nov 2026A large foundry says it wants inline optical test from visible to telecom wavelengths, which is a buyer-side signal for photonic test, though not yet proof that a new entrant wins it.
  • 23 Oct 2026Testing photonic chips is a real bottleneck for co-packaged optics, and the test-equipment incumbents have already bought or built their way into it. The new companies in the category have raised almost nothing.
  • 21 Jul 2026There is no agreed way to test an optical switch or chip, unlike a transceiver, and nobody has characterised the failure modes. Three separate companies independently say the real obstacle to shipping photonics is not performance but proving the parts still work after a few years in a rack — and the answer is redundancy rather than perfect components.