Theses›Datacentre & AI compute›Datacentre thermal materials

Datacentre thermal materials

AI accelerator thermal management does not converge on a single winning material through 2030.

  • Closing
  • $19B by 2035

The call, a draftThe segmentation read is winning: packages past 1.5kW need a different material at each thermal layer, and no material is close to dominating. The window is late, because coolant channels etched into the silicon threaten the premium layer.

Disclosure: TrimTabs, one of the companies named here, pays me to write a newsletter for it.

D1D2D3D4R1R2R3C1C2C3foragainst D1D2D3D4R1R2R3C1C2C3foragainst
Fig. 1The balance. Drivers and catalysts against restraints, each block sized by its weight; catalysts hang dashed because they have not happened yet, sized by their odds. It tips toward the drivers.
  1. D1NVIDIA's Rubin at 1,800-2,300W forces material-specific redesigns at the die-attach, lid, spreader and rack at once.
  2. D2The TIM decision is split between chip makers, foundries, assembly houses and system builders, and 6-12 month qualification runs punish every new material, so no single buyer can move the whole stack onto one material.
  3. D3Element Six and Orbray reached a 50mm single-crystal synthetic diamond wafer above 2,200 W/mK in Oct 2025, and Samsung has filed on a diamond-in-metal heat spreader for AI packaging.
  4. D4Solving the die moved the hard problem to the power converters beneath it, which run at 82-88% efficiency in a 2mm height budget and reach 145C unmanaged, adding another layer.
  5. R1NVIDIA and TSMC are putting coolant micro-channels on the silicon for about 2,000W parts, and Microsoft's in-chip microfluidics removed heat up to 3x better than cold plates, which moves value into the die and away from premium interface materials.
  6. R2With both mating faces polished to about 1nm, the die-level interface becomes a flatness filler, so the premium on that slot erodes.
  7. R3Embedded microchannels already cut a 1kW converter block from 145C to 84C in published work, so the same fix follows the heat to each new layer.
  8. C1Direct-to-chip liquid cooling is specified in more than half of new AI training builds of 50MW or more.31 Dec 2027
  9. C2A mainline AI accelerator shipping over 1M units a year carries a diamond-composite or other >700 W/mK spreader as standard.31 Dec 2030
  10. C3AI and HPC thermal management revenue passes $25B with no material class above 40% of premium stack revenue.31 Dec 2030
Rests onthe beliefs underneath
Supported by · confidence
What would prove itdated tests, open and resolved
20272028202920302031today1234567predictionswatch 20272028202920302031today1234567predictionswatch
Fig. 2Each ring is a dated test: dashed while open, struck through when overdue, ticked or crossed once resolved.
  1. 1Direct-to-chip liquid cooling reaches >50% of new AI training builds by 2027.Dec 2027 · open
  2. 2How fast coolant micro-channels in the silicon move from NVIDIA's top part into mainline accelerators.Dec 2027 · open
  3. 3Total AI accelerator thermal management market reaches $25B+ by 2030.Dec 2030 · open
  4. 4No single material captures >40% of premium thermal stack revenue by 2030.Dec 2030 · open
  5. 5Two-phase immersion cooling stays under 15% of new AI builds by 2030.Dec 2030 · open
  6. 6Whether any one material passes 40% of premium thermal-stack revenue.Dec 2030 · open
  7. 7Whether two-phase immersion stays under 15% of new AI build capacity.Dec 2030 · open
Expressionslisted, private, technologies
Private · 24 private companies, 11 of them in the US.

EMCOOL · SHT Smart High-Tech · Qnity Electronics · Arieca · NovoLinc · Element Six (De Beers Group) · Boston Materials · TrimTabs · NAWAH · Carbice · Akash Systems · CMatrics · Diamond Foundry · Element Six · Iceotope Technologies · Submer · Jetcool Technologies · Zutacore · Aavid (Boyd Corporation) · Honeywell · Thermaflux · Elephantech · HyMet Thermal Interfaces · SCD Technology Ltd

16 more private companies tracked, not shown

Technologies
What changedthe record, newest first
  • 2 Sep 2026The published record on AI power delivery says something the cooling argument mostly skips. The hard thermal problem in a modern accelerator is no longer the processor, it is the last power-conversion stage underneath it, running at 82-88% efficiency inside a 2mm height budget and reaching 145C with nothing done about it. Solving the die did not solve the system, it moved the problem one layer down, which is evidence for the view that thermal management stays segmented layer by layer instead of converging on one winning answer. The uncomfortable half is that the same embedded-microchannel approach that solved the die also works at the new layer, so the relief travels with the problem, and I have not improved my odds on the non-convergence part because of it.
  • 2 Sep 2026A deposition-tool startup has put a real number on low-temperature deposition, 70C over 5 hours with no cooling, and is pitching thermal layers grown inside the chip stack rather than bolted on at the back end. If it works that is another contender in accelerator thermal management, not a winner, which is what this page has argued all along: the stack stays segmented through 2030.
  • 13 Aug 2026Even cooling architectures that put a cold plate inside the chip package still need a thermal interface material against the die, because the packaging supply chain cannot bond silicon to silicon.
4 earlier
  • 31 Jul 2026A foundry packaging voice confirmed the thermal stack has no single decision-maker — chip IDMs, fabless designers, assembly houses and system builders each own different interfaces — and that qualification mechanics punish every new material equally, which is why the stack keeps segmenting rather than converging on one winner.
  • 29 Jul 2026Samsung has filed on a diamond composite heat spreader for AI accelerator packaging, while no foundry appears to be filing on integrated diamond deposition, which is consistent with the thermal stack staying segmented by integration point.
  • 13 Jul 2026A wafer-scale AI compute architecture already carries a dedicated cooling wafer in its stack — die-level thermal is becoming a designed-in layer of the compute stack, not an afterthought bolted on at the package.
  • 3 Jul 2026A diamond vendor argued the multi-material case against his own interest: diamond only pays at the very top power tier, his own composite serves the cost tier, and carbon nanotubes win where reworkability and vacuum matter. The thermal stack is segmenting by physics, not converging on a winner.
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