Theses›Defence & security›Hardware memory safety

Hardware memory safety

Hardware-enforced memory safety, capability silicon in the CHERI / CHERIoT lineage, becomes a required layer for security-critical and legacy-C/C++ compute as memory-safety mandates bite.

  • Bear
  • Early
  • $380B by 2035

The callRust meets the memory-safety mandate more cheaply than CHERI hardware, and no mandate names hardware, so capability silicon stays grant-funded.

D1D2D3R1R2R3C1foragainst D1D2D3R1R2R3C1foragainst
Fig. 1The balance. Drivers and catalysts against restraints, each block sized by its weight; catalysts hang dashed because they have not happened yet, sized by their odds. It tips toward the restraints.
  1. D1About 70% of serious security bugs are memory-safety bugs, and billions of lines of C and C++ will never be rewritten; Rust covers only new code.
  2. D2Capability hardware makes whole attack classes impossible in the processor, with legacy C running on a recompile and a provable guarantee for certification.
  3. D3The policy push is real: the White House ONCD report, CISA and NSA guidance.
  4. R1No mandate names hardware; the guidance points at software first and treats hardware as the route for legacy code only.
  5. R2Arm, Apple and Microsoft give the primitive away, and Arm ended Morello saying it has no plan to put it in any product.
  6. R3The best exit in the lane is Secure Thingz to IAR for about $35M, and the reachable market is under $1B through 2030.
  7. C1A tier-1 MCU vendor or Arm shipping a production CHERI-style part, or SCI winning a named production design-in; the first would also shrink the startup slice.end-2027
Rests onthe beliefs underneath
Supported by · confidence
What would prove itdated tests, open and resolved
202720282029today123watch 202720282029today123watch
Fig. 2Each ring is a dated test: dashed while open, struck through when overdue, ticked or crossed once resolved.
  1. 1ST, NXP, Infineon, Microchip or Arm shipping a CHERI-style part in production.Dec 2027 · open
  2. 2The first commercial CHERI chipmaker announcing a named production customer.Dec 2027 · open
  3. 3Any mandate that names hardware rather than outcomes; Rust satisfying the mandates first is the standing bear.Dec 2028 · open
Expressionslisted, private, technologies

2 more private companies tracked, not shown

Technologies
What changedthe record, newest first
  • 4 Nov 2026The people building memory-safe chips say buyers still think a 5% speed cost is too much to pay for removing a whole class of bugs.
  • 4 Nov 2026Memory-safe hardware is becoming a standard option on open chips, and European liability rules are what will make buyers pay for it.
  • 2 Nov 2026Even engineers building memory-safe chips say the hard part is not the technology but finding a business model that IP licensing has not already failed at.
2 earlier
  • 23 Oct 2026I score hardware memory safety at 20. It fixes the bugs AI finds fastest, but almost none of this month's breaches came through that door, and nobody is being made to buy the chips.
  • 23 Oct 2026Memory-safe code would have stopped the PHP bug and maybe two others out of 24. The rest came through stolen passwords and poisoned updates. Memory safety is one fix for one class, not the fix.