Atomic layer deposition (ALD) (process step)

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last updated 2026-06-20 · +1 sources in last 30d
ALD (Atomic Layer Deposition) ALD (Atomic Layer D… Atomic la…

Step 28 of 56 in the semiconductor flow (FEOL). Prev: CVD / PECVD deposition (process step) · Next: PVD / sputtering (process step)

What this step does

ALD builds ultra-thin films one atomic layer at a time. Unlike CVD, where precursors react continuously, ALD splits the reaction into self-limiting half-cycles separated by inert-gas purges, so each pulse deposits exactly one monolayer no matter the surface shape. That gives near-perfect thickness control (sub-nanometre) and conformality on the vertical, high-aspect-ratio structures that define modern logic and memory. Sub-processes inside the step:

Where it sits and why it matters

ALD is the fastest-growing deposition technique because the industry is going vertical. Gate-all-around (GAA) transistors at 2nm wrap the gate around stacked nanosheets, 3D DRAM and ever-taller 3D NAD multiply the number of conformal-film steps, and self-aligned patterning offloads cost from EUV onto deposition. Each of these raises “ALD intensity,” the number of ALD layers per wafer. ASM estimates the GAA and FinFET-in-periphery transition alone adds US$400-450M to its served market [1]. ALD is the technique that scales with vertical complexity, which is why it outgrows CVD and PVD.

Equipment market

The cleanest figure comes from ASM’s 2025 Investor Day: the single-wafer ALD market grows from US$3.0B (2024) to US$5.1-6.1B by 2030, a 9-13% CAGR [1]. Adding batch ALD and broader definitions, third-party reports put total ALD equipment at roughly US$4-9B in 2024-2025 at 10-17% CAGR; that spread reflects inconsistent report-mill scoping, so treat the ASM single-wafer figure as the anchor [1][2].

Vendor HQ Est. share Notable
ASM International Netherlands mid-50s% single-wafer ALD [3] Gold standard for logic high-k ALD; Pulsar / Synergos platforms
Kokusai Electric Japan ~70% batch ALD [4] Batch furnaces for 3D NAND / DRAM; KKR-backed 2023-24 IPO
Tokyo Electron (TEL) Japan #2 batch, growing single-wafer [4] Strong memory and patterning film position
Lam Research US ~34% ALD-dielectric memory penetration [3] High-aspect-ratio gapfill / dielectric ALD
Applied Materials US minority, scaling [3] Acquired Picosun (2022); GAA and 3D DRAM R&D push

Concentration is high: the four WFE incumbents (AMAT, ASM, TEL, Lam) plus Kokusai hold roughly 72% of revenue [3], and the market splits cleanly by segment, ASM owning single-wafer logic, Kokusai owning batch memory.

Volumes, revenue, profitability

The revenue pool splits two ways. Tools are a lumpy ~US$5-6B equipment market that follows fab capex cycles; precursors are a smaller ~US$1B but stickier, recurring stream. The economics are excellent for the lead vendor: ASM posted FY2024 adjusted gross margin of 50.5% and adjusted operating margin of 28.0% on EUR2,933M revenue, and grew faster than WFE [6][1]. ASM’s 2030 plan targets revenue above EUR5.7B at a 12%+ CAGR versus ~6% for the broader WFE market, explicitly an outperformance story driven by ALD intensity [1]. The margin accrues to the equipment vendor that owns the qualified process recipe at a given node, not to the fab or the precursor chemist; switching a qualified ALD recipe is slow and risky, which is the moat.

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