Physics / mechanism
Multi-Project Wafer (MPW) runs multiple chip designs on a single wafer by partitioning the reticle field — typically 26×33 mm for EUV, larger for older nodes — among several customers, each paying a fractional share of mask and fab costs. A full mask set at TSMC N5 runs $5–15M; MPW reduces per-project NRE to $50K–500K depending on process node and die area. Shuttle runs are batched periodically (monthly to quarterly). Key parameters: reticle utilisation, shuttle cadence, PDK access, and test vehicle availability. GF, TSMC, Europractice (imec/IHP), SkyWater, and Tower all run commercial MPW programmes. EDA tool compatibility and DRC sign-off are gating constraints.
Competitive landscape
Dedicated wafer runs (full production) are the alternative once yield and volume justify it; breakeven typically hits at 5K–50K units depending on die area. ASIC prototyping via PCB + FPGA bridges early feasibility but cannot validate analogue, RF, or photonic performance. SiPh-specific MPW (AIM Photonics, imec, CEA-Leti, Cornerstone) compete with CMOS-node shuttles for photonics teams. Open-source PDKs (SkyWater 130nm, GF 180nm) lower the floor further.
Relation to the PDK
Companies using
Connected ideas
Sources
Frontier (open questions)
- To be added.