Why it has become a gating parameter rather than a nuisance: as logic moves to gate-all-around nanoribbons and complementary FETs (CFETs), channel widths fall into the tens of nanometres and channel resistance falls with them, so the fixed contact term comes to dominate total device resistance. Atomically thin transition-metal dichalcogenide (TMD) channels are attractive for those architectures because a sub-nanometre body suppresses leakage, but there is very little material into which to inject carriers. A 2026 trade analysis lists contact resistance, weak p-type behaviour and integration as the three blockers keeping TMD channels out of production ref. The same analysis notes copper interconnect hitting its own nanoscale resistance wall, with ruthenium and molybdenum offering large reductions in ultra-fine lines, so the resistance problem is arriving at both ends of the wire-to-channel path.
Contact resistance is not only a logic problem. A diamond Schottky PIN diode reporting ~116 kA/cm2 and 0.05 mOhm-cm2 specific on-resistance identifies defect density and contact resistance as the two terms that must fall for the device to approach its theoretical material limit. Interfacial charge-transfer resistance is also the framing concern in electrode/electrolyte pairing for solid oxide cells, where surface energy and roughness descriptors are proposed as early screens.
Evidence base
Open questions
Assessment drafted 2026-08-31 from up to 11 KB sources using the technology-scorecard framework; scores are a draft read pending review.
Recent mentions
2026-10-12Carbon nanotube electronics: market, cohort and M&A research (web sweep, 82 sources)web
What p-type contact resistance, in ohm-micrometres and at a stated channel length, has actually been measured for WSe2 or another TMD, and how far is it from the value the self-consistent model says is needed to avoid source-limited saturation below 10 nm 2026 08 10 ultralow p type contact resistance for ultra nanoscaled 2d m?
Do the contact schemes implied by the MIGS dimensionality scaling law survive foundry constraints on thermal budget, contamination and wafer-scale uniformity, or do they only work in single-device demonstrations 2026 06 16 contacts to low dimensional semiconductors physical theory a?
Does the width-scaling benefit observed in 30-40 nm MoS2 nanoribbons persist when channel length is also scaled, where the fixed contact term dominates total resistance 2026 05 05 scaling two dimensional semiconductor nanoribbons for high p?
How much of the diamond diode's gap to its theoretical limit is attributable to contact resistance rather than defect density, and which is the cheaper term to reduce 2026 07 02 diamond diode for extreme venus environments?
What's the current best contact resistance achieved at 2nm-node by TSMC / Intel / Samsung internally?
How much of the 35–40% contact-resistance fraction is recoverable in production (vs theoretical)?
Which foundry signs the first IP licence for a new contact material? When?
Are alternative-silicide solutions (NiSi₂, CoSi₂, replacement-metal-gate variants) already addressing this internally?