Trends›Lithography tools become the bottleneck
Lithography tools become the bottleneck
From ~2029, ASML's Low-NA EUV tool output (not packaging or memory) becomes the binding constraint on leading-edge AI-chip capacity, because ASML can build only ~100 machines a year against the ~3.5 EUV tools needed per gigawatt of compute, so the bottleneck migrates upstream from CoWoS/HBM…
74 ↑3 confidence, computed 23 Oct 2026
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What rests on thismarkets it underwrites or threatens
Evidencethe schedule the figure draws
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- Oct 2026
for · observable ASML says its currently planned supply for 2027 and 2028 will not fully meet customer demand, even with a planned 30% increase in low-NA EUV and DUV immersion capacity in 2027 and a further ~30% being investigated for 2028; some… ASML Q3 2026 financial results (Form 6-K press release) - Jun 2026
for · observable Multi-patterning Low-NA EUV stays cost-competitive vs High-NA for 1.4nm/14A — leading-edge nodes consume MORE Low-NA passes per wafer, raising tools-per-wafer demand and tightening Low-NA tool supply even if High-NA is deferred. ASML Dilemma — Multi-Patterning Low-NA EUV vs High-NA (SemiAnalysis) - Jun 2026
against · observable TSMC confirmed it bought High-NA EUV (~$400M/tool) for R&D only and will not deploy in mass production until at least 2029 on cost — so the gating tool on the largest foundry's leading edge is Low-NA EUV multi-patterning, not High-NA… TSMC defers High-NA EUV mass production to ~2029 on cost (TrendForce) - Apr 2026
against · observable ASML plans to produce 60 EUV systems in 2026, increasing to 80 units, falling materially short of the ~100 systems threshold. ASML increases production of EUV systems amid growing demand for AI chips - Apr 2026
for · primary CoWoS advanced packaging bottleneck persists through 2026 with TSMC capacity sold out; constraint stays in packaging, not lithography. AI Semiconductor Supply Chain: The Bottleneck Has Shifted - Apr 2026
for · primary TSMC defers High-NA EUV to 2029+ and plans multi-patterning with Low-NA EUV through A13 node, validating the narrow-form weakness. ASML's High-NA EUV Ambitions Meet a TSMC Reality Check - Apr 2026
against · observable ASML guided to ship 'at least 80' Low-NA EUV systems in 2027, more than double the 44 shipped in 2025, with production targets of 90 Low-NA EUV and 600 DUV systems annually — output is ramping, not frozen. ASML targets >doubling EUV output by 2027 (The Elec, citing Q1 2026 call) - Apr 2026
for · observable ASML reported a record EUV backlog of 45 units and EUR38.8B total backlog in Q1 2026 and raised FY2026 guidance to EUR36-40B, with TSMC/Samsung/Intel ordering for 2nm-and-below — demand visibly outrunning current tool output. ASML Q1 2026: record EUV backlog of 45 units, EUR40B guidance raise - Mar 2026
for · primary Patel: ~3.5 EUV tools per gigawatt; ASML makes ~70 tools now, ~80 next year, only a little over 100 by end of decade; ~700 cumulative tools implies a ~200GW AI ceiling; 'by 2028 or 2029 the bottleneck falls to the… Dylan Patel (SemiAnalysis) on Dwarkesh Podcast — the 3 big bottlenecks to scaling AI compute - Mar 2026
against · claim Analysts (Future Horizons) warn AI-driven semi demand is concentrated and a correction is 'inevitable,' with 2026 growth forecasts 12-18% (down from ~22% in 2025) — a demand-digestion scenario would relieve tool-supply pressure before litho becomes binding. Warning signs / 2026 overcapacity-and-digestion debate (eeNews / Future Horizons) - Jan 2026
for · claim Intel installed its second High-NA EXE tool and made 14A the first 'High-NA native' node — High-NA entering the leading-edge critical path, though concentrated in one early adopter. Intel installs second High-NA EUV; 14A 'High-NA native' - Jan 2026
for · claim TSMC is doubling CoWoS capacity annually through end-2026 (toward ~1M wafers vs ~370k in 2024) — packaging aggressively de-bottlenecked while EUV output rises only ~20-30%/yr, so the constraint plausibly migrates upstream to litho. TSMC doubling CoWoS capacity through 2026 (packaging de-bottlenecking) - Dec 2025
neutral · primary Epoch AI: in 2025 the top-4 AI designers consumed >90% of global CoWoS + HBM by value but only ~12% of advanced logic die production — confirming the 'from' state (packaging/HBM is the 2025 constraint, not litho), the premise for… Packaging and HBM, not logic dies, were the 2025 AI-chip bottleneck (Epoch AI) - Nov 2024
neutral · observable ASML's own 2030 model projects EUR44-60B revenue at double-digit EUV-spend CAGR across litho-intensity scenarios — a large but bounded tool installed base; the high end requires litho-intensity rising, the very mechanism that makes tools binding. ASML Investor Day 2024 — 2030 revenue EUR44-60B, EUV double-digit CAGR
What would move itthe measures watched
- watchASML annual Low-NA EUV system shipments (units/yr). 44 in 2025, ~60 guided 2026, target 'at least 80' in 2027, ceiling ~90-100/yr even under aggressive expansion. Run-rate plateauing near 100 while AI wafer demand climbs = litho binding; ASML materially above 100/yr = thesis weakens.
- watchASML EUV order backlog / book-to-bill. Backlog lengthening faster than output expands = demand outrunning tool supply (for); falling book-to-bill = digestion (against).
- watchEUV tools required per GW of AI compute vs ASML output. SemiAnalysis frames ~3.5 EUV tools/GW; ~700 cumulative tools by 2030 implies a ~200GW AI ceiling. Rising litho-intensity (more multi-patterning, HBM wafer-area) tightens the constraint.
- watchBinding-constraint location: CoWoS/HBM vs logic-litho. 2025 constraint was packaging/HBM. Migration to litho confirmed when CoWoS lead times shorten (currently 52-78wk) while EUV remains the gating step.
- watchHigh-NA EUV adoption on the leading-edge critical path. Intel deploying High-NA on 14A; TSMC defers HVM use to ~2029 on $400M cost. If TSMC stays on multi-patterning Low-NA, the binding tool is Low-NA EUV, not High-NA.