A SPAD is a reverse-biased semiconductor diode operated above breakdown so that a single absorbed photon triggers a self-sustaining avalanche and a clean digital pulse, giving CMOS image sensors photon counting with picosecond-class timing and no readout noise; the device physics is now largely solved and the binding constraints have shifted to dead time, off-chip data bandwidth and wavelength coverage beyond silicon.
Summary
A single-photon avalanche diode is a photodiode biased beyond its breakdown voltage. A single photo-generated carrier initiates an avalanche that saturates the junction, producing a digital pulse rather than an analogue photocurrent. The avalanche must then be quenched and the pixel recharged, and during this dead time the pixel is blind. Because the output is a timestamp or a count rather than an integrated charge, SPAD arrays detect individual photons at each pixel with extreme temporal resolution and without readout noise, which is why they are the sensor of choice for low-light imaging and time-resolved measurement. They are also natively digital optical interfaces, which makes them unusually well suited to logic processing and event-driven computation placed directly next to the pixel.
The parameters that decide a SPAD are photon detection efficiency (PDE), dark count rate (DCR), afterpulsing probability, dead time, timing jitter, and array format. State of the art in silicon is strong: a thick-junction, backside-illuminated Si SPAD with a 50 V quenching readout has been reported at 84.4% PDE at 785 nm with 260 cps dark count rate and 2.9% afterpulsing at 268 K, in a compact module supporting free-running, gated and hybrid operation. Silicon’s bandgap, however, caps sensitivity short of telecom wavelengths. Two routes are being pursued: germanium-on-silicon SPADs for the shortwave infrared, which moved from a first cryogenic demonstration in 2011 to a room-temperature demonstration in 2024, and non-avalanche alternatives such as a black-phosphorus (~350 meV absorber) van der Waals heterojunction detector aimed at room-temperature 1550 nm operation, positioned explicitly against InGaAs SPADs’ lower efficiency, high dark counts, afterpulsing and fabrication hazards.
Two non-negotiable physical limits shape system design. First, dead time: at high photon flux a SPAD saturates, losing photons within a symbol (blocking loss) and smearing across symbols (inter-symbol interference), a problem now being modelled in closed form via renewal theory for slow regimes and Markov chains for regimes where symbol duration is shorter than dead time. Second, data volume: high-resolution SPAD arrays can generate tens of gigabytes per second of timestamps, so the output path, not the detector, sets the achievable resolution.
Consequently much of the current work is architectural rather than device-level: statistical sketch compression on FPGA achieving 512x compression against conventional histogram output on a 192 x 128 array, removal of time-to-digital converters altogether in favour of per-pixel spike encoders feeding spiking neural networks, moving FPGA-style look-up-table logic on-chip at pixel or cluster level, and generative reconstruction of images from sparse binary quanta frames using adapted latent diffusion models.
Evidence base
- A thick-junction, backside-illuminated Si SPAD module reached 84.4% photon detection efficiency at 785 nm with a 260 cps dark count rate and 2.9% afterpulsing at 268 K, using a 50 V quenching readout (published 24 July 2025).
- GeSi SPADs progressed from a first cryogenic SWIR single-photon demonstration in 2011 to a room-temperature demonstration in 2024 (review, 8 May 2026).
- High-spatial-resolution SPAD arrays can produce tens of gigabytes per second of timestamps; an FPGA sketch implementation on a 192 x 128 array achieved 512x compression versus conventional histogram output with histogram-free online depth reconstruction (11 February 2026).
- Transporter, a 128 x 4 SPAD sensor with per-pixel D flip-flop ring spike encoders, eliminates time-to-digital converters and histogramming in favour of in-sensor spike encoding for spiking neural networks (7 November 2025).
- Dead time imposes both intra-symbol blocking loss and inter-symbol interference in SPAD-array optical wireless receivers, modelled exactly by renewal theory below dead time and by a Markov chain above it (28 May 2026); a companion paper proposes automatic attenuation control with a low-complexity variant cutting computation by two orders of magnitude (28 May 2026).
- Long-term parallel operation of SiPM modules and PMTs in the MAGIC 17 m telescope camera showed SiPMs deliver only comparable performance to PMTs despite higher PDE, motivating the use of SPADs as truly digital sensors (23 February 2026).
- A 64 x 64 perimeter-gated SPAD array in 0.35 µm CMOS achieved under 1% bias variation at 2 kHz per pixel and passed all 16 NIST Statistical Test Suite tests after Von Neumann debiasing (18 June 2025), and the same array class ran the Probabilistic Approximate Optimization Algorithm on 26-spin Sherrington-Kirkpatrick instances with up to 17 layers (15 February 2026)
Open questions
- Do the in-sensor processing architectures (spike encoders, on-chip LUT logic) preserve depth and photometric accuracy when scaled from 128 x 4 and 192 x 128 formats to large-format arrays, or does per-pixel logic area collapse fill factor?
- Can room-temperature SWIR photon counting in GeSi reach the PDE, dark count and afterpulsing figures already achieved in silicon at 785 nm, and at what yield in a standard CMOS flow?
- Does dead-time mitigation, whether by automatic attenuation control or statistical correction, hold up in real high-background field conditions such as daylight LiDAR, rather than in the analytical and numerical models presented?
- Will simulated datasets and diffusion-model priors close the training-data gap well enough that models trained synthetically transfer to real SPAD data across sensors and light levels, or does each sensor need its own captured corpus?
Assessment drafted 2026-08-31 from up to 18 KB sources using the technology-scorecard framework; scores are a draft read pending review.