An avalanche photodiode is a reverse-biased semiconductor detector in which impact ionisation gives internal gain; biased past breakdown it becomes a single-photon avalanche diode (SPAD) that turns one photon into a digital pulse, and because it can be built in standard CMOS it is now the default building block for photon-counting arrays in LiDAR, quantum optics and low-light imaging.
Summary
An avalanche photodiode (APD) is a photodiode operated at high reverse bias, where photogenerated carriers are accelerated hard enough to knock further carriers out of the lattice. That impact-ionisation cascade provides internal gain. Push the bias above breakdown and the device enters Geiger mode: a single absorbed photon triggers a self-sustaining avalanche, producing a large digital pulse that must then be quenched before the pixel can fire again. The device in this mode is a single-photon avalanche diode (SPAD). The physics of the multiplication step is still being refined; a 2026 paper argues that the usual semiclassical treatments (local ionisation coefficients, Monte Carlo trajectories) break down in nanoscale high-field junctions and reformulates impact ionisation as a multi-particle self-energy in a non-equilibrium Green’s function framework.
The parameters that decide a SPAD are: photon detection efficiency, dark count rate, dead time after each avalanche, afterpulsing, and the wavelength reach set by the absorber bandgap. Silicon SPADs are mature, run at room temperature and are CMOS-compatible, but their bandgap stops them well short of the 1550 nm telecom band; InGaAs SPADs reach 1550 nm but with lower efficiency, higher dark counts and afterpulsing. Germanium-on-silicon is the CMOS-friendly route into the shortwave infrared, moving from a first cryogenic demonstration in 2011 to a room-temperature demonstration in 2024. A third route sidesteps the detector entirely by converting infrared photons up into the visible and counting them with a silicon device, either via nonlinear frequency upconversion or via two-photon absorption inside the silicon APD itself.
The active research frontier is no longer the single diode but the array and what sits underneath it. SPADs are natively digital, so pixel-level logic is natural: recent work puts active quenching and digital readout in a 40 nm CMOS SPAD array, replaces per-pixel time-to-digital converters with spike encoders for neuromorphic processing, and moves FPGA-style look-up-table reconfigurability onto the sensor die. That is driven by a hard engineering constraint: a 192 x 128 SPAD array streaming timestamps can generate tens of gigabytes per second.
Two secondary uses exploit the device’s imperfections rather than its sensitivity. Dark-signal non-uniformity across a perimeter-gated SPAD imager has been used as a physically unclonable function for image watermarking, and the same 64 x 64 array’s dark-count randomness has been used as a source of stochastic p-bits for a probabilistic optimisation algorithm.
Evidence base
- Ge-Si SPADs moved from a first cryogenic demonstration in 2011 to a room-temperature demonstration in 2024, per a review published 8 May 2026.
- A mid-infrared upconversion detector reported 4 June 2026 achieved 80% conversion efficiency at 3 µm, 37% overall detection efficiency, noise equivalent power of 1.8 x 10^-17 W/Hz^1/2, and photon-number resolution up to 9 with 0.14% noise probability per pulse when paired with a silicon APD.
- Non-degenerate two-photon absorption in a silicon APD pumped at 3 µm, reported 3 June 2026, raised signal counting rate by a factor of about 10^5 and improved noise equivalent power by two orders of magnitude over near-infrared pumping, at room temperature.
- An FPGA sketching implementation for a 192 x 128 SPAD LiDAR array, dated 11 February 2026, achieved 512x compression versus histogram output, addressing timestamp data rates that can reach tens of gigabytes per second.
- A 40 nm CMOS SPAD array with on-chip active quenching and digital readout, reported 24 February 2026, supports an estimated magnetic field sensitivity of approximately 90 nT/√Hz per pixel for NV-centre widefield ODMR biosensing.
- A 64 x 64 perimeter-gated SPAD array in 0.35 µm CMOS ran the Probabilistic Approximate Optimization Algorithm on 26-spin Sherrington-Kirkpatrick instances using dark-count stochasticity as p-bits, reported 15 February 2026.
Open questions
- What are the dark count rate, photon detection efficiency and afterpulsing figures of room-temperature Ge-Si SPADs relative to InGaAs SPADs, and are they good enough to displace them in SWIR imaging?
- Does on-chip processing (sketching, spike encoding, embedded LUT logic) scale from the 192 x 128 and 128 x 4 formats demonstrated to megapixel arrays without prohibitive pixel-area or power cost?
- Can dead-time mitigation schemes such as automatic attenuation control survive real deployment conditions, or does the count-rate ceiling remain the binding limit on SPAD data rates in optical wireless and LiDAR?
- Which mid-infrared route wins on cost and integrability: direct absorber SPADs, nonlinear upconversion into silicon devices, or non-avalanche room-temperature detectors such as van der Waals heterojunctions?
Assessment drafted 2026-08-31 from up to 18 KB sources using the technology-scorecard framework; scores are a draft read pending review.