NAND flash is the non-volatile memory behind all solid-state storage; its economics now hinge on whether stacking more device layers still cuts cost per bit (a 2013 model says no, past a point) and whether the array itself can be turned into a search engine for data-movement-bound workloads.
Summary
NAND flash stores bits as charge (or, in newer variants, ferroelectric state) in transistor cells wired into long series strings. Because cells share a string rather than each getting its own contact, NAND achieves the highest bit density and lowest cost per bit of any manufactured memory, at the price of slow, block-granular erase and page-granular access. Planar scaling stopped paying, so the industry moved to 3D: the string is stood on end and threaded through a stack of deposited device layers, etched in one go. The main vertical-channel families are BiCS, p-BiCS and TCAT Walker 2013 Rigorous 3D Nand Flash Cost Analysis.
The governing parameter for 3D NAND economics is not layer count on its own but the geometry of the deep etch. Every high-aspect-ratio etch has a non-zero taper angle, so the memory hole and the slit are wider at the top of the stack than at the bottom, and it is the top-of-stack pitch that gets projected onto the wafer and sets the array footprint. Walker’s model shows that pitch grows linearly with layer count, carrying a term 2·N_L(L_g + L_s)·tanθ in the Y-pitch. Two effects therefore fight: more layers means fewer cells per layer, so footprint should shrink, but each layer widens the top-of-stack cell, so footprint grows. They cross. The consequence is a minimum in die cost per bit at some layer count, after which adding layers makes the die more expensive, contradicting the monotonic-improvement premise on which vertical-channel 3D NAND was sold. Walker further argues that a lithography-intensive layered approach, using three critical masks per device layer, can reach a smaller die and undercut the vertical-channel route on total cost Walker 2013 Rigorous 3D Nand Flash Cost Analysis.
The second live question is what NAND is for beyond storage. Two 2026 computer-architecture papers treat the NAND array as compute substrate. A cross-platform survey of accelerators for open modification search in mass spectrometry, a workload dominated by reference data movement rather than arithmetic, benchmarks 3D NAND and FeNAND in-storage processing against GPUs, near-storage FPGAs, DRAM near-memory processing and ReRAM/PCM in-memory processing under consistent algorithmic and accuracy assumptions, using a binary hyperdimensional computing formulation that tolerates device non-idealities. D-NOVA goes further and embeds an inverted-file retrieval pipeline directly into the NAND array with a distance metric, Dual-Bound Tight Similarity Sensing, designed for the string structure, on the grounds that existing in-storage accelerators still spend nearly 70% of retrieval time on host or embedded processors outside the memory.
One caveat on evidence: most of the supplied source set concerns photonic bound states in the continuum and is unrelated to NAND flash beyond an acronym collision with BiCS. Only three sources bear on this page, and they constrain what can honestly be scored below.
Evidence base
- November 2013: a peer-reviewed cost model shows vertical-channel 3D NAND (BiCS, p-BiCS, TCAT) has a minimum in die cost per bit versus layer count, after which cost rises with every added layer, contradicting the monotonic-improvement premise the architecture was sold on Walker 2013 Rigorous 3D Nand Flash Cost Analysis.
- The mechanism is geometric: non-zero etch taper angle θ makes the top-of-stack cell pitch grow linearly with layer count, via the term 2·N_L(L_g + L_s)·tanθ in the Y-pitch, so array footprint growth eventually beats the per-layer cell saving Walker 2013 Rigorous 3D Nand Flash Cost Analysis.
- The same analysis argues a lithography-intensive layered 3D approach, at three critical masks per device layer, can reach a smaller die and undercut vertical-channel 3D NAND on total cost Walker 2013 Rigorous 3D Nand Flash Cost Analysis.
- 21 July 2026: D-NOVA reports that existing in-storage retrieval accelerators still spend nearly 70% of total retrieval time on host or embedded processors outside the memory, and responds by embedding an IVF retrieval pipeline and a string-tailored distance metric (Dual-Bound Tight Similarity Sensing) into the NAND array.
- 21 July 2026: the first workload-driven cross-platform survey of mass-spectrometry search accelerators benchmarks 3D NAND and FeNAND in-storage processing against GPUs, near-storage FPGAs, DRAM near-memory processing and ReRAM/PCM in-memory processing, using a binary hyperdimensional computing formulation chosen to tolerate device-level non-idealities.
Open questions
Assessment drafted 2026-08-31 from up to 18 KB sources using the technology-scorecard framework; scores are a draft read pending review.