Physics / mechanism
Spin-orbit-torque magnetic random-access memory (SOT-MRAM) writes a magnetic tunnel junction by passing charge current through an adjacent spin-orbit coupling layer, which converts it into a transverse spin current that exerts torque on the free layer. This separates the write path from the read path in the conventional three-terminal geometry. The two-terminal variant (2T-SOT-MRAM) collapses the device back to a single current path, trading write-path independence for cell area and array simplicity comparable to spin-transfer-torque (STT) MRAM.
The decisive parameter is the character and efficiency of the torque generated by the SOT layer. Physical modelling of 2T-SOT-MRAM indicates that SOT materials producing only in-plane torque give little to no write-energy improvement over STT-MRAM, because the in-plane torque cannot efficiently initiate switching of a perpendicular free layer without additional field or symmetry breaking. Emerging materials that supply an out-of-plane torque component change the picture: out-of-plane SOT efficiencies as low as 0.1 yield significant write-energy reductions in two-terminal devices.
The benefit strengthens with scaling. Improvements are most pronounced when the magnet lateral dimensions are reduced to 30 nm or 20 nm, since the switching energy of the free layer falls faster than the parasitic cost of driving current through the SOT layer. A proposed device geometry lengthens the path electrons take through the SOT layer, raising the generated spin current per unit charge current and hence the energy efficiency.
Benchmarking places the target: an out-of-plane SOT efficiency of 0.051 in a 20 nm-wide device gives write energies approaching SRAM at the 7 nm technology node. This is the figure of merit that determines whether SOT-MRAM can displace SRAM in last-level cache rather than only competing with embedded flash.
Competitive landscape
The direct comparison supported by the sources is against STT-MRAM, which shares the two-terminal cell topology and the magnetic tunnel junction stack. On write energy, 2T-SOT-MRAM with conventional in-plane-torque SOT materials offers no clear advantage over STT-MRAM; the differentiation depends entirely on securing out-of-plane torque materials. The further-out target is SRAM-class write energy, which the modelling reaches only under specific assumptions of 20 nm device width and out-of-plane SOT efficiency of 0.051 at the 7 nm node. Three-terminal SOT-MRAM is the implicit alternative within the SOT family, offering decoupled read and write paths at the cost of cell area; the sources here address the two-terminal case specifically.
Evidence base
- Modelling published 5 December 2025 finds that common SOT materials providing only in-plane torque give little to no write-energy improvement over STT-MRAM in two-terminal devices.
- Emerging SOT materials with out-of-plane torque efficiencies as small as 0.1 produce significant write-energy improvements in 2T-SOT-MRAM.
- The advantage is strongest when magnet lateral dimensions scale to 30 nm or 20 nm.
- A proposed 2T-SOT device increases the electron path length through the SOT layer, raising generated spin current and energy efficiency.
- Benchmarking indicates out-of-plane SOT efficiency of 0.051 at 20 nm device width yields write energies approaching SRAM at the 7 nm node.
Frontier (open questions)
- Which material systems actually deliver out-of-plane SOT efficiency at or above 0.051, and are they compatible with back-end-of-line CMOS thermal budgets?
- Does the extended-electron-path device geometry survive fabrication at 20 nm, and what is the measured rather than modelled spin-current gain?
- What are the write error rate and switching time distributions of 2T-SOT-MRAM at 20 to 30 nm, which the write-energy benchmarking does not address?
- How does retention and thermal stability of the free layer hold up at 20 nm lateral dimension, where the modelled energy advantage is largest?
Synthesised 2026-08-31 from 1 KB sources by the resynth pipeline; citations are KB source slugs.