An open interconnect standard that lets hosts pool, expand and share DRAM across a fabric (CXL memory expanders, smart-memory controllers, switches). Rides the HBM-scarcity / disaggregated-memory why-now, but the value sits at the controller/standards/system layer (Astera Labs, Marvell, Panmnesia, Montage) — out of the device/materials mandate; routed to a software-layer fund.
Concept stub created 2026-06-03 from the semi+photonics gap-map research (segment backfill).