Silicon germanium is a strained, lattice-mismatched alloy of silicon and germanium grown epitaxially on silicon wafers, and it has become the load-bearing substrate for two very different things at once: stacked-channel logic beyond the 2 nm node, and the leading semiconductor spin-qubit platforms.
Summary
Silicon and germanium are both group IV, fully miscible, and share the diamond lattice, but germanium’s lattice constant is about 4% larger. Alloying them (Si1-xGex) therefore gives a continuously tunable lattice constant and a continuously tunable band structure, which can be grown by chemical vapour deposition on standard silicon wafers. Two consequences follow. First, a thin layer grown on a mismatched template holds strain pseudomorphically, so you can strain a silicon channel (higher electron mobility) or a germanium channel (higher hole mobility) by sandwiching it between SiGe barriers. Second, silicon and SiGe etch at very different rates in the same chemistry, which is what makes stacked nanosheet and multi-channel logic architectures manufacturable: grow a Si/SiGe superlattice, then selectively remove the SiGe to release suspended silicon channels.
The same heterostructure toolkit produces the substrate for spin qubits. A thin strained Si quantum well between relaxed SiGe barriers hosts a two-dimensional electron gas with low charge noise and, with isotopic purification of 28Si, a very quiet nuclear environment. Invert the strain and you get Ge/SiGe, hosting a two-dimensional hole gas with strong intrinsic spin-orbit coupling that permits all-electrical qubit driving. First-principles work on tailored strained-Si/SiGe interfaces finds that band alignment depends sharply on composition: below roughly 25% Ge there is no conduction band offset, so only a hole gas can form, while above it either a 2DEG or a 2DHG is possible, with carriers confined to two or three atomic layers of the interface.
The parameters that decide SiGe are all about disorder and thermal budget rather than about the idea. Germanium fraction sets strain, band offsets and valley splitting. Growth temperature sets Ge-Si interdiffusion: a segmented temperature-control scheme reported in 2026 lowered the Ge diffusion coefficient to 5.6-7% of its 650 C value, giving a 4 + 4 channel stack with fully coherent strain, 1.5-2.6 nm interface transition widths and 0.08 nm RMS roughness, though the bottom of the stack still saw Ge dilution from 20% to 18.5% from cumulative thermal exposure. Metamorphic buffers relax the mismatch by generating dislocations, and those dislocations do not stay put: X-ray nano-mapping of an Intel Si/SiGe qubit chip resolved crosshatch fine structure and permanently distorted lattice planes propagating through the heterostructure at 30 nm lateral and 200 nm depth resolution, with a calculated effect on qubit energy spectra.
For the alloy in its bulk role, random substitutional disorder is the dominant phonon scatterer, which is why SiGe is a thermoelectric material as well as a logic material; a 2026 substitutional atomic distance model reproduces measured SiGe thermal conductivities and attributes the reduction chiefly to alloy scattering.
Viability (4/5)
Evidence of working devices is broad. Ge/SiGe hole spin qubits have been operated with radio-frequency single-shot readout and coherent control of two single-spin qubits using a global accumulation gate and only single-layer depletion fine gates, with coherence times and exchange tunability comparable to conventional overlapping-gate devices. Planar germanium quantum wells have been demonstrated with hole mobility of 1.3 x 10^6 cm^2/Vs and survive a 500 C anneal alongside an integrated superconductor with Tc around 1.85 K and out-of-plane critical field up to 1.9 T. On the logic side, coherent 4 + 4 channel Si/SiGe superlattices with sub-3 nm interface widths have been grown.
What holds the score below 5 is that the failure modes are now well characterised and unsolved. Growth of SiGe unavoidably introduces dislocations, inhomogeneous strain and crosshatch, expected to cause device-to-device fluctuation and qubit failure. Random alloy disorder spatially randomises valley splitting and valley phase in Si/SiGe, making the electric-dipole spin resonance Rabi frequency position-dependent, and g-factor mapping over a 40 nm x 400 nm area resolves two distinct valley-related g-factors per dot site with a bimodal distribution. In germanium, site-to-site variation of the qubit sweet spot is identified as an obstacle to maintaining fidelity across a wafer. Individual devices work; statistically identical devices do not yet exist.
TLDR: The material works and is being grown in industrial fabs; the open problems are uniformity and thermal budget, not feasibility.
Drivers (4/5)
Demand pull is visible on two independent axes. Logic: stacking multiple Si/SiGe channels is the route to advanced nodes, and the growth work is framed explicitly as establishing a material foundation for logic devices beyond the 2 nm node. Quantum: silicon quantum dot spin qubits are pursued for their small size and compatibility with industrial semiconductor manufacturing, and Si/SiGe heterostructures are the common host because of high mobility and low percolation density. A third, smaller driver is heteroepitaxy: ultra-thin SiGe metamorphic buffers are being developed as strain-relieving templates for wafer-scale III-V integration on silicon for optoelectronics.
On the supply side, the sources show capability rather than economics. An Intel Si/SiGe qubit chip was available for destructive-free X-ray structural mapping, Si/SiGe field-effect stacks are being produced and characterised in a fab-style research pipeline, and isotopically enriched 70GeH4 precursor has been used to grow a high-quality 2DHG. None of the supplied sources give wafer costs, precursor supply constraints, epi tool capacity or isotope enrichment volumes, so the economics of scaling supply cannot be assessed here.
TLDR: Demand is structural, from both logic scaling and spin qubits; the sources say nothing about cost, capacity or market size.
Novelty (3/5)
Judged as a material, SiGe is decades-old and its advantages over bulk silicon (strain engineering, selective etch contrast, tunable band offsets) are established rather than new. The interesting question is what the 2026 variants are better than. Against plain Si/SiGe: Wiggle Wells introduce deliberate Ge concentration oscillations to enhance Dresselhaus spin-orbit coupling so that qubits can be driven electrically without external micromagnets, and the baseline they improve on is weak, since intrinsic Rashba spin-orbit coupling in Si/SiGe is small enough that a coherent chirality-induced spin selectivity signal would exceed it by two orders of magnitude. Against non-purified germanium: isotopic enrichment with 70GeH4 suppresses nonzero-spin nuclei and improves T2* at the sweet spot, following the precedent set by 29Si depletion in silicon.
The architectural gains are sometimes larger than the materials gains. Swapping the roles of overlapping nanogates in Si/SiGe improved exchange coupling tunability by several orders of magnitude over the traditional approach, a fix for the fact that the SiGe spacer physically separates qubits from control electrodes. Gate-biased near-infrared illumination made per-gate operating voltages uniform and small in a triple dot without changing measured charge noise. Notably, both are workarounds for SiGe’s own liabilities rather than intrinsic advantages of the alloy, which is why the score sits at 3.
TLDR: SiGe itself is an incumbent material; the novelty is in engineered variants that beat plain Si/SiGe on specific defects.
Diffusion (4/5)
SiGe faces almost none of the classic new-material adoption barriers. It is a group IV alloy grown by CVD on silicon wafers in existing tools, compatibility with industrial semiconductor manufacturing is one of the stated reasons for choosing it as a qubit host, and industrial Si/SiGe qubit chips already exist. Fabrication complexity is being reduced rather than increased: single-layer fine-gate Ge/SiGe devices with a global accumulation gate match overlapping-gate performance while cutting multi-layer patterning and overlay requirements, explicitly to widen access for smaller groups. Superconducting contacts compatible with the thermal budget of strained germanium epitaxy have been demonstrated.
The barriers that remain are process-control barriers. In logic, cumulative thermal budget across a stack degrades the layers grown first, with measurable Ge dilution and broadened interfaces at the bottom of a 4 + 4 stack. In qubits, disorder from the gate stack couples to the quantum well and its strength depends on well depth and electrostatic charge history, and characterisation at 1.5 K does not fully capture what happens at millikelvin operating temperatures. Scalable spin shuttling over micrometres requires the electron to traverse angstrom-scale disorder without leaking into valley-excited states, which sets hard constraints on acceptable atomistic disorder in the conveyor-belt architecture. Diffusion of the material is not in doubt; diffusion of yield is.
TLDR: Already inside industrial CMOS lines, which removes the usual barrier; the residual barrier is wafer-scale uniformity, not fab acceptance.
Impact (4/5)
If Si/SiGe superlattice growth holds strain and interface quality through the full thermal budget of a multi-channel process, it is the enabling layer for stacked-channel logic beyond 2 nm. That is a large and non-substitutable role: the selective-etch contrast between Si and SiGe is what makes released stacked channels manufacturable at all. Separately, if the disorder problem is solved, Si/SiGe and Ge/SiGe are the substrates for spin-qubit architectures that inherit CMOS manufacturing economics, including shuttling-based connectivity for efficient quantum error correction.
There is optionality beyond those two. Proximitised Ge/SiGe quantum dots show multi-level pi-junction Josephson behaviour previously seen mainly in exceptionally clean systems such as carbon nanotubes, establishing proximitised germanium as a hybrid superconductor-semiconductor platform with a route to topological devices. SiGe buffers are a candidate path to monolithic III-V on silicon photonics, and alloy scattering makes SiGe a thermoelectric material whose thermal conductivity can be tuned compositionally. Impact is not 5 only because in the logic role SiGe is an enabler of a scaling step rather than the source of the value, and in the qubit role the value is contingent on an unresolved disorder problem.
TLDR: It sits under two roadmaps that both matter: sub-2 nm logic channels and semiconductor spin-qubit scaling.
Timing Soon (2-5yr)
For logic, the work is already at the stage of establishing process-physics understanding of thermal budget in multi-channel superlattices, framed against nodes beyond 2 nm. That is a 0-5 year industrial timeframe rather than a research question. For qubits, the 2026 literature is dominated by diagnosis rather than solution: mapping g-factors and intervalley coupling, depth-resolving lattice distortions in an industrial chip, and quantifying how much atomistic disorder a shuttling architecture can tolerate.
That diagnostic phase is a necessary precursor and a good sign, but the sources show two-qubit demonstrations rather than uniform arrays, and the mitigations on offer are per-device tuning procedures such as gate-biased illumination rather than growth changes that remove the variability at source. Expect the material question in quantum to be settled on a 5-10 year horizon, with the logic question settled sooner.
TLDR: Logic epitaxy is at process-development maturity now; the qubit role is gated by wafer-scale uniformity and is further out.
Overrated or underrated? Underrated
SiGe reads as boring infrastructure, and that is precisely why it is underrated. The 2026 literature makes a consistent case that in silicon and germanium spin qubits the rate-limiting variable is no longer gate design or control electronics but the atomistic state of the alloy: random alloying randomises the Rabi frequency, growth dislocations create permanently distorted lattice planes that shift qubit energy spectra, and shuttling fidelity is set by angstrom-scale disorder encountered over micrometres. Anyone modelling spin-qubit scaling as a control-engineering problem is modelling the wrong bottleneck.
The corollary is that the interesting investable and publishable work is metrology and epitaxy, not qubit counts. Techniques that resolve strain at 30 nm laterally through a working chip, g-factor variation to better than 10^-3, and millikelvin disorder signatures that 1.5 K screening misses are the tools that will decide whether the platform yields. The counter-argument to the call: SiGe is already in production for logic and its adoption there is uncontroversial, so the underrating claim rests specifically on the quantum use case, where the disorder problem might not be solvable by growth at all.
Prediction
No Si/SiGe or Ge/SiGe spin-qubit device with more than 50 quantum dots operating at uniform, individually untuned gate voltages will be reported in the peer-reviewed or arXiv literature before 31 December 2028.
Evidence base
- Segmented temperature control lowered the Ge diffusion coefficient to 5.6-7% of its 650 C value, producing a 4 + 4 channel Si/SiGe stack with fully coherent strain, 1.5-2.6 nm interface transition widths and 0.08 nm RMS roughness, though bottom-layer Ge fell from 20% to 18.5%, published 8 May 2026
- X-ray nano-structural mapping of an Intel Si/SiGe chip at 30 nm lateral and 200 nm depth resolution revealed extended growth dislocations creating permanently distorted lattice planes and crosshatch fine structure, with calculated impact on qubit energy spectra, 30 July 2026
- Two-dimensional mapping of electron g-factors in planar Si/SiGe quantum wells to better than 10^-3 precision across a 40 nm x 400 nm area found two valley-related g-factors per dot site with a bimodal distribution, 27 July 2026
- Ge/SiGe hole spin qubits with a global accumulation gate and single-layer depletion fine gates achieved RF single-shot readout and coherent control of two single-spin qubits with coherence and exchange tunability similar to overlapping-gate devices, 8 July 2026
- A planar germanium quantum well retained 1.3 x 10^6 cm^2/Vs hole mobility after 500 C annealing while integrated with a PtIrSiGe superconductor of Tc ~1.85 K and out-of-plane critical field 1.9 T, 11 August 2026
- First-principles hybrid DFT of strained-Si/SiGe interfaces found no conduction-band offset for Ge fraction below 0.25, precluding a 2DEG at low Ge content, with carriers confined to 2-3 atomic layers of the interface, 30 June 2026
Open questions
- Can growth changes remove the crosshatch and dislocation-induced strain that X-ray mapping found propagating through an industrial Si/SiGe heterostructure, or will per-device tuning such as gate-biased illumination remain necessary indefinitely?
- Does the segmented-temperature growth approach hold coherent strain and 20% Ge concentration through the full downstream thermal budget of a real sub-2 nm logic flow, not just an 8-layer test stack?
- Is random alloy disorder in the SiGe barrier an intrinsic, irreducible floor on valley-splitting and g-factor variation, or can engineered composition profiles such as Wiggle Wells trade it for something more tolerable?
- Does the Ge/SiGe hole-qubit route, with isotopic 70Ge purification and simplified single-layer gating, overtake Si/SiGe electron qubits on wafer-scale uniformity, given that hole sweet spots also vary site to site?
Assessment drafted 2026-08-31 from up to 18 KB sources using the technology-scorecard framework; scores are a draft read pending review.