Physics / mechanism
Low-k dielectrics are insulating materials placed between metal interconnect layers in ICs to reduce parasitic capacitance (C = εₒκA/d). Lower dielectric constant (κ) cuts RC delay and dynamic power dissipation — critical as nodes shrink and interconnect dominates performance. Standard SiO₂ has κ ≈ 3.9; production-grade fluorinated silicate glass (FSG) reaches ~3.5; carbon-doped oxides (CDO/SiOCH) used in volume at 28nm–7nm hit κ ≈ 2.5–2.9. Porous ultra-low-k (ULK) films push κ below 2.5 by introducing controlled porosity (15–50%), trading mechanical strength (hardness drops to ~1–2 GPa vs. ~8 GPa for SiO₂) for electrical performance. Integration challenges — moisture uptake, CMP damage, plasma-induced degradation — are unsolved at leading edge.
Competitive landscape
Competing approaches include airgap interconnects (κ ≈ 1.0, used selectively by Intel/TSMC at 10nm+, integration complexity is high), metal-organic frameworks as next-gen porous dielectrics (lab-stage, κ < 2.0), and self-assembled nanoporous silica. Adjacent materials include high-k gate dielectrics (HfO₂, κ ~20–25) — opposite problem, different stack location. Spin-on dielectrics (SOD) compete with CVD-deposited ULK for gap-fill applications.
Companies using
Connected ideas
Sources
Frontier (open questions)
- To be added.