RF Soi

last updated 2026-08-31

Physics / mechanism

The supplied source set does not describe the device physics of RF SOI (radio-frequency silicon-on-insulator). No substrate resistivity figures, switch on-resistance/off-capacitance (Ron*Coff) targets, harmonic-distortion specifications, or process-node details for the platform appear in the material available for this page.

What the sources do establish is the platform context. GlobalFoundries frames its 2026 strategy around “Physical AI” organised into sense / think / act / communicate, and positions itself as a “feature-rich, not node-leading” specialty foundry rather than a leading-edge logic competitor ref. RF connectivity sits inside the “communicate” pillar of that framing, alongside the compute and embedded-memory pillars that the deck documents in more detail.

The same deck names a specialty process portfolio spanning FDX, FinFET and BCD platforms, with an embedded non-volatile memory offering (eMRAM, ReRAM, FLASH) layered across them ref. RF SOI is not enumerated in the excerpt available here, so its relationship to those platforms, and any co-integration of RF front-end and embedded memory on a single die, is undocumented in these sources.

Competitive landscape

No comparison is supportable from the supplied sources. The only positioning claim available is company-level: GlobalFoundries describes itself as a specialty foundry competing on feature richness rather than transistor density, with FY2025 financials and 2028 targets organised around Physical AI end markets ref. Competing RF SOI suppliers, wafer vendors, substrate types (trap-rich vs high-resistivity) and alternative front-end technologies (GaAs, SOI CMOS vs bulk CMOS switches) are not covered by anything cited here.

Evidence base

Frontier (open questions)

Synthesised 2026-08-31 from 1 KB sources by the resynth pipeline; citations are KB source slugs.

Recent mentions

Frontier questions