EDA is the software layer that turns design intent into manufacturable silicon, and the 2026 research front is rebuilding it around large language models, differentiable optimisation and surrogate models, with benchmark results showing real gains in design turnaround but verification quality still well short of sign-off.
Summary
Electronic design automation (EDA) covers the tool chain between a designer’s intent and a manufacturable chip: writing register transfer level (RTL) code in Verilog, SystemVerilog or VHDL, verifying it, synthesising it, placing and routing it, estimating power and timing, laying out analog blocks, and exploring architectures before any of that is committed. Each of those stages is currently a mix of solver-based algorithms, hand-tuned heuristics, slow simulators and large amounts of manual engineering judgement.
The current wave of work attacks this from three directions. First, LLMs as code and property generators: RTL generation with tool assistance and curated datasets, VHDL generation and evaluation infrastructure built by automatically converting Verilog designs and testbenches into executable VHDL benchmarks validated with VUnit/GHDL, hierarchical formal verification via generated SystemVerilog Assertions, and full analog flows that carry design intent through topology synthesis, sizing and constraint-driven layout. Second, learned or differentiable replacements for expensive inner loops: source-level module power estimation without simulation at inference time, Gaussian-reparameterised differentiable operator scheduling for compilation and high-level synthesis, and neural surrogates plus a decision-tree quality gate for signal-integrity-compliant PCB interconnect design. Third, modelling tools for physical realities the existing tools were never built for: inter-die routing in 2.5D and 3D FPGAs, modelled by extending the open-source VTR/VPR flow with HSPICE circuit models of a 7 nm die on a 45 nm interposer, and embodied plus operational carbon as a first-class architectural metric.
The parameters that decide whether any of this matters are unglamorous. For generative tools, everything hinges on whether the output is checked by a real tool rather than scored by string similarity: compile rate, proof success, vacuity, mutation coverage and formal core coverage are the numbers that separate a demo from usable automation. For surrogate tools, it is whether accuracy holds across configurations and workloads outside the training distribution. For both, the binding constraint is training and evaluation data, which is why several of these papers are data synthesis pipelines rather than models. And for anything touching a real tape-out, the question is whether the result can be signed off, which none of the supplied sources demonstrates.
Evidence base
- Across twelve recent LLMs, generated SystemVerilog Assertions achieved a 67.1% module-level compile rate, 82.1% non-vacuous proof rate, detection of only 70.2% of eligible injected faults and 36.2% formal core coverage on a 342-module hierarchical dataset.
- An LLM-enhanced analog framework spanning topology synthesis, sizing and layout reports turnaround falling from days or weeks to hours while improving design performance.
- Fine-tuned LLM shuttling compilers for trapped-ion machines generated valid schedules for circuits up to 16 qubits, generalised to an unseen four-way junction layout, and cut shuttling effort by up to 15% versus state-of-the-art baseline compilers.
- The open-source VTR flow was extended with HSPICE models of inter-die connections on a 7 nm process and a 45 nm silicon interposer, because the absence of accurate modelling tools had left most 2.5D and 3D routing architecture questions unanswered.
- Architecture Carbon Tool v3, published June 2026, frames sustainability as a system architecture design metric requiring a new generation of EDA and architectural modelling tools, and adds first-order design space exploration.
- A differentiable scheduling framework using Gaussian reparameterisation reduced the optimisation space by orders of magnitude versus categorical formulations and gave the first differentiable formulation of pipelined scheduling, reaching Pareto-optimal results.
Open questions
- Do LLM-generated assertion sets close the gap between proving non-vacuously (82.1%) and covering the formal core (36.2%), or is the missing coverage a structural limit of generating properties without a specification the model can be held to?
- Does PANDA’s reported reduction of analog turnaround from days or weeks to hours reproduce independently, on production process design kits rather than research flows?
- How far do surrogate power models such as BigPower degrade outside their training configurations and workloads, and is the residual error small enough to make architectural decisions on?
- Will the small synthesised datasets now being published (342 modules in HierSVA-DS, Verilog-to-VHDL conversions in VHDLSuite) scale to the volume needed for fine-tuning, or does the field remain data-limited?
Assessment drafted 2026-08-31 from up to 18 KB sources using the technology-scorecard framework; scores are a draft read pending review.