GaN-on-Si

last updated 2026-05-04

Physics / mechanism

GaN grown epitaxially on large-diameter silicon substrates (200 mm dominant, 300 mm emerging). The lattice mismatch (~17%) and thermal expansion mismatch require buffer layer stacks—typically AlN nucleation + graded AlGaN—to manage threading dislocation density (~10⁸ cm⁻²) and wafer bow. The active device exploits the AlGaN/GaN heterointerface: spontaneous + piezoelectric polarisation induces a 2DEG with sheet carrier density ~10¹³ cm⁻² and electron mobility ~2000 cm²/V·s. Breakdown fields reach 3.3 MV/cm. Key figures of merit: R_on·A ~1–5 mΩ·cm² for 650 V devices; switching frequencies into MHz range. Dominant applications: power conversion (EV onboard chargers, data-centre PSUs, PFC), RF front-ends. Leading fabs: Infineon, STMicro, TSMC, GlobalFoundries, Wolfspeed (on SiC not Si), Transphorm, Navitas.

Competitive landscape

GaN-on-SiC is the direct competitor for RF and high-power density applications—lower dislocation density, superior thermal conductivity (490 W/m·K vs 150 for Si), but 4× wafer cost and smaller diameter cap scalability. GaN-on-Si trades thermal headroom for CMOS-fab compatibility and cost. Silicon MOSFETs (SJ, superjunction) compete below 600 V on cost. SiC MOSFETs compete above 900 V on temperature tolerance.

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Frontier (open questions)

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