The structural reason analog computing companies die. The simulator (FDTD electromagnetic, SPICE circuit, or whatever physics model the architecture uses) predicts one thing; the fabricated chip behaves differently. The gap is typically 5-15% of the modelled response, and that delta often eats the entire performance claim the company is built on.
The pattern
Every analog accelerator company follows the same trajectory:
- Architecture validated in simulation — clean ODE / circuit model produces ideal results
- First silicon (or PCB) arrives — measured response differs from simulation
- Per-chip calibration burden discovered — every fabricated unit needs its own correction profile
- Drift discovered — temperature, age, bias history all move the calibration target
- Calibration latency dominates — the correction loop eats the headline speed claim
- Pivot, downsize, or die
Notable casualties
| Company | Substrate | Outcome | Cause |
|---|---|---|---|
| Mythic AI | Analog flash matrix-mul | Pivoted, downsized | Per-cell conductance drift + die-to-die variability eroded the analog speedup |
| HP Labs memristor | Resistive RAM crossbars | Team disbanded | Sneak paths, write variability, decade of papers without commercial scale |
| Lightelligence | Photonic Ising → photonic matmul | Pivoted to interconnect | Mach-Zehnder interferometer mesh calibration at scale |
| Lightmatter (early) | Photonic Ising machine | Pivoted to optical matrix-mul, then interconnect | Same MZ calibration class |
Notable survivors (and how they survived)
| Company | Substrate | Survival mechanism |
|---|---|---|
| Ntt Research CIM | Photonic OPO + fibre loop | Pushed calibration into digital measurement-feedback at ms latency; works but loses 1000x on per-solve time |
| D Wave Systems | Cryogenic superconducting | Different physics class — calibration happens via slow annealing, not a fast realised-J target |
| Toshiba SBM, Fujitsu DA | Digital simulation of Ising | Avoided the wall by not building analog hardware |
DD signals to listen for
- “We’ve simulated the calibration loop end-to-end including realistic noise and drift” → strong
- “FPGA pre-distortion is in the M1 milestone” without algorithm spec → weak
- “We’ll figure it out at scale” → fatal
- “Each chip needs ~1 hour of VNA calibration” → operational but tractable
- “Each chip needs days of calibration” → not viable at production volume
- “Calibration drifts daily with temperature” → unworkable for edge deployment