Timing / Clock Generation

Physics / mechanism

Clock generation converts a reference oscillator into the timing signals that synchronise digital, RF, and mixed-signal systems. The core chain: a reference (crystal, MEMS, or atomic resonator) feeds a phase-locked loop (PLL) or delay-locked loop (DLL), which multiplies frequency and reduces jitter. Key parameters are phase noise (dBc/Hz at offset frequencies), RMS jitter (femtoseconds to picoseconds), frequency range, and lock time. State of the art: silicon TCXO references at ±0.5 ppm stability; integrated PLL jitter floors ~50 fs RMS in 7 nm FinFET; photonic-based optical frequency combs pushing sub-femtosecond jitter for defence and metrology applications.

Competitive landscape

Dominant incumbent approach is quartz crystal + CMOS PLL (SiTime, TXC, Microchip/Vectron). MEMS oscillators (SiTime, Resonant/Murata) displace quartz in harsh environments with better shock/vibration resilience. Photonic frequency combs (Octave Photonics, imec spin-outs) target datacentre co-packaged optics and radar but remain expensive. Atomic clocks (Microsemi, Orolia) address GNSS-denied navigation. The real competitive axis is jitter floor vs. integration level vs. cost.

Companies using

Connected ideas

Sources

Frontier (open questions)

• To be added.