Physics / mechanism
A SerDes (serialiser/deserialiser) is the mixed-signal circuit block that converts a wide, slow parallel bus inside a chip into a small number of very high-rate serial lanes for transmission off-die, and reverses the conversion at the receiver. It is the electrical layer that sits underneath chip-to-chip, package-to-package and rack-scale interconnect standards, and in optical links it is the block that drives and recovers data from the electro-optical front end.
The headline parameter is per-lane signalling rate, quoted in Gb/s. MediaTek’s offer to Google for TPU v9 was reported as a 336G SerDes solution, i.e. a per-lane rate of 336 Gb/s ref. Aggregate interface bandwidth is the lane rate multiplied by lane count; the same report describes MediaTek design wins framed at 2.4T, the aggregate scale at which accelerator interconnect is now specified ref.
Competitive landscape
The sources support only a narrow view: SerDes as merchant IP supplied into custom accelerator programmes, where winning the interface block is a route into a large ASIC design win. MediaTek’s 336G offering is presented as the lever that secured Google TPU v9 orders, implying competition is between IP vendors on lane rate and readiness rather than between architectures ref. No source here compares electrical SerDes against co-packaged optics or other optical-interconnect approaches, so the position of SerDes relative to those alternatives is not established by this evidence base.
Evidence base
Frontier (open questions)
Synthesised 2026-08-31 from 5 KB sources by the resynth pipeline; citations are KB source slugs.