Optical I/O at Chip Level

last updated 2026-05-04

Physics / mechanism

Optical I/O at chip level replaces copper bumps or wirebonds with photonic links integrated at the package edge or directly on-die, moving data as photons rather than electrons. Key components: laser source (on-chip VCSEL or hybrid III-V), modulator (ring resonator or Mach-Zehnder), waveguide (SiN or Si), and photodetector. Bandwidth density target is >1 Tb/s/mm²; current co-packaged optics (CPO) hits ~3.2 Tb/s per device at <5 pJ/bit. On-die integration (monolithic or 3D-bonded) pushes toward <1 pJ/bit. Principal bottleneck: laser integration on silicon—hybrid bonding of InP dies is the leading workaround. Intel IPG, Ayar Labs, Ranovus, and Broadcom are primary execution benchmarks.

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