Physics / mechanism
CMOS image sensors (CIS) convert photons to charge via the photoelectric effect in silicon photodiodes, then read out voltage using in-pixel source-follower transistors. The dominant architecture is backside-illuminated (BSI) stacked CIS, where the photodiode layer is flip-bonded to a logic wafer carrying ADCs and ISP logic—decoupling pixel pitch scaling from readout circuit area. Key parameters: quantum efficiency (peak ~80–90% at 550 nm in BSI), read noise (<1e⁻ in scientific CMOS), full-well capacity, dynamic range, and dark current density. Leading nodes: Sony Semiconductor, Samsung, OmniVision on 90–45 nm CIS-optimized processes. Pixel pitches now reach 0.56 µm (mobile) to 3.45 µm (machine vision). Stacked 3D integration (Cu-Cu hybrid bonding) enables >1 Gpixel/s readout.
Competitive landscape
CIS competes with and complements several sensor modalities. CCD retains niche dominance in astronomy and medical imaging due to lower fixed-pattern noise. SPAD arrays challenge CIS in low-light and LiDAR time-of-flight applications. InGaAs focal plane arrays own SWIR (900–1700 nm) where silicon is blind. Emerging alternatives include perovskite and organic photodetector layers that could be monolithically integrated on CMOS logic wafers, threatening the silicon absorber layer specifically.
Companies using
Connected ideas
Sources
Frontier (open questions)
- To be added.