Design

RTL to tape-out: synthesis, place-and-route, timing signoff, verification, DFT, IP licensing, OPC. Where a chip exists only as software.

13 concepts in this cluster

Clock tree synthesis (process step)

+2 sources in 30d

Design-for-test (DFT) (process step)

+2 sources in 30d

Floorplanning & power planning (process step)

+2 sources in 30d

Functional verification & emulation (process step)

+2 sources in 30d

Logic synthesis (process step)

+4 sources in 30d

Mask data prep & computational litho (OPC/ILT) (process step)

+2 sources in 30d

Physical verification (DRC/LVS/DFM) (process step)

+2 sources in 30d

Placement (process step)

+15 sources in 30d

Product specification & architecture (process step)

+2 sources in 30d

Routing (process step)

+14 sources in 30d

RTL design (HDL) (process step)

+2 sources in 30d

Semiconductor IP licensing (process step)

+2 sources in 30d

Timing signoff & parasitic extraction (process step)

+2 sources in 30d