Silicon spin qubits encode quantum information in single electron spins held in gate-defined quantum dots on silicon chips, betting that CMOS foundry manufacturing beats every other qubit platform on scaling; foundry-made devices have now reached coherent operation of eight qubits, with two-qubit gate fidelity and device-to-device variability the unresolved blockers.
Summary
A silicon spin qubit is a single electron (or hole) trapped in an electrostatically defined quantum dot in a silicon device, with the two spin states serving as the computational basis. Dots are formed and tuned by metal gates on top of a silicon channel, exactly the structure of a MOSFET: the 2026 eight-qubit demonstration describes an eight-dot linear array tuned as four double-dot pairs, fabricated in a 300 mm CMOS-compatible foundry process. Two-qubit gates come from the exchange interaction between neighbouring dots, controlled by the voltage on the barrier gate between them. Readout is done by charge sensing; the eight-qubit device used a cascaded charge-sensing protocol to measure the central four qubits.
The platform’s appeal is twofold. First, coherence: isotopically purified, nuclear-spin-free silicon is intrinsically favourable for electron spin qubits, and the foundry device showed Ramsey dephasing times up to 41(2) microseconds and Hahn-echo coherence up to 1.31(4) milliseconds. Second, manufacturability: the claim throughout the literature is that spin qubits can leverage the existing semiconductor infrastructure rather than build a new one.
The parameters that decide the technology are all noise and uniformity parameters. Charge noise, widely attributed to individual two-level fluctuators in the oxide and interfaces, is the dominant performance limit; under a strong magnetic field gradient it is transduced into magnetic noise and destabilises qubit operation on timescales comparable to data acquisition. Uniformity is the second axis: three-dimensional device simulation of nanosheet double dots finds that millivolt-level bias variation on plunger and middle barrier gates is enough to push two-qubit gate fidelity below 99%. Because nearest-neighbour exchange only connects adjacent dots, architectures add coherent electron shuttling to move spins between distant patches, as in the shuttling-based SpinBus design and hybrid shuttling-connected patch layouts studied for magic-state distillation.
Evidence base
Open questions
- What two-qubit gate fidelity is achieved on 300 mm foundry-fabricated devices, and how does it vary across dies and wafers rather than within a single hero device?
- Do the noise-suppression techniques that delivered single-qubit fidelity above 99.6% under a strong field gradient extend to exchange-based two-qubit gates at the same overhead?
- Does coherent electron shuttling remain viable as the connectivity layer once the real two-level-fluctuator density along long channels is mapped?
- In the cross-platform energy efficiency framework, where do silicon spin qubits actually land relative to superconducting, trapped-ion, neutral-atom and photonic systems?
Assessment drafted 2026-08-31 from up to 10 KB sources using the technology-scorecard framework; scores are a draft read pending review.