Reversible Computing

Physics / mechanism

Landauer’s principle sets a thermodynamic floor: erasing one bit dissipates at minimum kT·ln2 (~3×10⁻²¹ J at 300 K). Conventional CMOS discards logical state at every gate transition, burning ~100–1000× that floor. Reversible computing preserves logical state through bijective operations—inputs recoverable from outputs—so entropy doesn’t increase and, in principle, energy can be recaptured. Implementations span adiabatic CMOS (charge recycled via resonant LC tanks, ~10–50% energy reduction demonstrated), quantum computing (inherently unitary/reversible gates), and ballistic/mechanical proposals. Practical adiabatic circuits operate at lower clock frequencies (MHz range vs. GHz) to allow quasi-static switching; the energy-delay product often fails to beat optimized conventional CMOS below ~10 nm nodes. No commercial silicon product ships as “reversible” today; best demonstrated systems are research-grade ASICs and FPGA overlays.

Competitive landscape

Adiabatic CMOS is the nearest practical path but competes directly with standard low-power design techniques—clock gating, power gating, near-threshold voltage operation—which achieve 10–100× dynamic power reduction without frequency penalties. Neuromorphic architectures (Intel Loihi, IBM NorthPole) attack the same energy-per-inference metric via sparsity rather than reversibility. Cryogenic RSFQ (rapid single-flux-quantum) logic is reversible-adjacent and achieves ~10⁻¹⁹ J/op but requires 4 K operation.

Companies using

Connected ideas

Sources

Frontier (open questions)

• To be added.