Physics / mechanism
RISC-V is an open-standard instruction set architecture (ISA) released under royalty-free licenses, originally from UC Berkeley (2010). Unlike proprietary ISAs, any entity can implement RISC-V cores without licensing fees. The base integer ISA is fixed; optional extensions (M, A, F, D, C, V for vector, etc.) are modular. Implementations span 32-bit microcontrollers to 64-bit server-class cores. Current SOTA: SiFive P870 at ~4 GHz on TSMC N3, competitive with Arm Cortex-A series on SPECint. Vector extension (RVV 1.0) enables AI/ML inference acceleration. Embedded cores (e.g., CV32E40P) run at sub-milliwatt budgets, dominant in IoT and secure enclaves.
Competitive landscape
Arm is the primary incumbent — same application domains, vastly larger software ecosystem, stronger per-core performance at advanced nodes today. x86 competes at server/desktop but is irrelevant in embedded. MIPS and PowerPC are legacy residuals. The real competitive axis is not ISA performance but ecosystem maturity and vendor lock-in tolerance.
| ISA | Licensing | Ecosystem maturity | Edge/IoT traction |
|---|---|---|---|
| Arm | Royalty-bearing | Very high | Dominant |
| RISC-V | Free/open | Growing fast | Strong, accelerating |
| x86 | Proprietary | High (server/PC) | Negligible |
Companies using
Connected ideas
Sources
Frontier (open questions)
- To be added.