Conventional digital logic (clocked CMOS processors, GPUs, FPGAs and fixed-function accelerators) remains the substrate on which essentially all computing is built, and the current research frontier has shifted away from faster arithmetic towards moving data less: chiplet-aware memory layouts, dual-mode reuse of existing arrays, and better simulation and measurement tooling.
Summary
What it is. “Conventional logic” is the mainstream computing substrate: Boolean gates implemented as clocked CMOS transistors, assembled into CPUs, GPUs, FPGAs and application-specific accelerators, and paired with a DRAM-based memory hierarchy. It is the baseline against which unconventional paradigms (quantum, spiking neuromorphic, analogue in-memory, physics-based annealers) are measured. The category is unglamorous precisely because it is universal, and the interesting question is not whether it works but where its remaining headroom lies.
How the headroom is now being extracted. A mid-2026 snapshot of computer-architecture research shows a consistent pattern: the wins no longer come from the logic itself but from three adjacent places. First, data movement and packaging. Multi-chiplet GPUs split memory into local and remote high-bandwidth memory across a silicon interposer, and remote traffic for a single matrix-multiply shape varies by up to 58x purely as a function of kernel and placement choices. Choosing a chiplet-contiguous global memory layout instead of fixed 4 KB page interleaving cuts remote traffic by 13.0x on Qwen 3 30B and 20.7x on Llama 3.1 70B matrix multiplications, with no operating-system or hardware changes. The same story appears in FPGAs, where die-stacking limits inter-die connection density and latency and therefore demands a bespoke inter-die routing architecture, and in DRAM, described as “the huge memory bottleneck that plagues modern computing systems”.
Second, reuse and specialisation of existing fabrics. Rather than building new cryptographic silicon, a dual-mode systolic array supports both matrix and direct polynomial multiplication for 20% extra area and negligible power overhead in matrix mode, beating transform-based polynomial multiplication on the same class of engine by more than 1.2x in latency. At the other end, fully custom conventional-logic chips still deliver: a 16 nm RISC-V system-on-chip with sixteen cores customised for Monte Carlo sampling, and a 65 nm probabilistic decision-tree engine at 11.3 nJ per inference with a 30-minute hypoglycaemia forecasting F1 of 0.825.
Third, tooling and observability. The design-space arguments above are only as trustworthy as the simulators behind them, which is why memory simulators are being rebuilt with HBM3/4, LPDDR5/6 and GDDR7 support plus formal validation workflows, and why power estimation is being pushed to source level using large-language-model representations of design hierarchy. The parameters that decide outcomes in this field are therefore: how much of the workload’s energy and latency is arithmetic versus movement, inter-die connectivity density and latency, arithmetic precision, and whether the software stack can express the optimal placement at all.
Evidence base
Open questions
- Do the 13x to 20x remote-traffic reductions reported for chiplet-contiguous layout convert into comparable end-to-end throughput or energy-per-token improvements on real inference serving, or are they absorbed by other bottlenecks?
- Will GPU and SoC vendors expose the CPU-side energy telemetry that already exists in firmware, given that an audit found per-rail energy computed internally but unreachable through any supported software interface?
- How far do inter-die connection density and latency limits constrain 3D stacked logic once real designs move beyond the simulated design-space exploration in the current FPGA modelling work?
- Does dual-mode reuse of AI matrix engines for cryptographic workloads scale beyond the 1.2x latency advantage shown at prototype level, or will dedicated accelerators reclaim the ground?
Assessment drafted 2026-08-31 from up to 18 KB sources using the technology-scorecard framework; scores are a draft read pending review.