CPU & SoC

Physics / mechanism

A CPU executes sequential instruction streams via fetch-decode-execute pipelines; an SoC integrates CPU cores alongside GPU, NPU, memory controllers, I/O, and analog blocks on a single die. Key parameters: clock frequency (3–5 GHz high-performance), IPC (instructions per cycle), core count, cache hierarchy (L1/L2/L3 latency and capacity), TDP, and process node. Leading-edge logic is at TSMC N3/N2, Samsung SF3, Intel 18A. Apple M4 (~3 nm class, ~120 TOPS NPU) and Qualcomm Snapdragon X Elite define current SoC integration density. Power-performance-area (PPA) trade-offs dominate design decisions at every node shrink.

Competitive landscape

The primary architectural competition is GPU (massively parallel, memory-bandwidth-bound workloads) and purpose-built accelerators (TPU, NPU, FPGA). At the chiplet/integration level, the contest is monolithic vs. disaggregated (UCIe, HBM stacking). RISC-V is eroding Arm’s ISA lock-in in edge/embedded.

Companies using

Connected ideas

Sources

Frontier (open questions)

• To be added.