Physics / mechanism
Licensable processor IP cores optimised for inference workloads. Cadence Tensilica HiFi/Vision DSPs use a VLIW + SIMD architecture with configurable instruction-set extensions; customers add custom functional units at RTL generation time, meaning MAC-array width, SRAM banking, and dataflow (weight-stationary vs output-stationary) are design-time parameters rather than fixed silicon. Arm Ethos-U55/U65/U85 targets Cortex-M-class systems; Ethos-U85 delivers up to 4 TOPS at sub-500 mW in 5 nm. Key figures of merit: TOPS/W, TOPS/mm², and supported operator coverage for ONNX/TFLite graphs. Both ship as synthesisable RTL licensed per-design or royalty-per-unit, targeting edge MCU and embedded SoC integrations rather than datacenter.
Competitive landscape
Competing IP blocks: Synopsys ARC NPX (tightly coupled NPU extensions on ARC scalar cores), CEVA NeuPro-S/M (streaming MAC arrays, strong in audio/vision fusion), Imagination IMG CXT (GPU-derived, broader operator coverage, higher area cost). Custom internal NPU teams at Apple, Samsung, and Qualcomm have made merchant IP less relevant at high volume. Chiplet and UCIe disaggregation is beginning to unbundle the compute tile from the IP licensing model entirely.
Companies using
Connected ideas
Sources
Frontier (open questions)
- To be added.